The biggest thing that sticks out to me is the pull up resistors. On the 20736S chips there are 10K pull up resistors external to the die. If you are pulling the line up on the other side, with a 4.7k, for instance, this may be detrimental to the timing of the I2C bus.
To my knowledge, there should be no activity on the i2c bus between nvram writes. I've had logic analyzers hooked up to a running app for hours without activity.
Do you get any successful reads/writes once the 20736S is connected (after init, to nvram, etc)?
Note here that the I2C spec requires an external pull up on SCL and SDA. The internal pullup is not sufficient because the part will not be configured until an I2C slave is detected (i.e. external pullup), which is a chicken-egg situation.
However, this only applies to the SoC. The pullups inside the SIP modules (shown on the internal schematic) are still external to the die, so the modules don't need pullups outside the module.
1. We don't support multi-Master I2C
2. Any pairing, calling NVRAM, OTA Upgrade, etc, there will be activity on the I2C bus
Thanks for the response. The issue happens upon POR when both sides a MCU and the BCM2073xS are initializing as we also initialize some sensors. For this sensor platform I have added a switch to disconnect the BCM2073xS I2C from the Sensor Board I have developed if the MCU is the I2C Master.
Yes, the switch is a good idea.