4 Replies Latest reply on Mar 5, 2020 10:11 PM by NoAr_1540581

    About tOHC spec for CYUSB3014

    NoAr_1540581

      Hello


      Asynchronous SRAM timing is used by using CYUSB3014. However, since tOHC is 0.5ns on the customer's system, the operation can not be guaranteed because the spec described in the data sheet can not be satisfied.
      Also, If tOHC (OE # HIGH to CE # HIGH) is not satisfied, they are understanding that as a result of CE # going high, They believe that the accuracy of the READ data cannot be guaranteed.
      Therefore, I understand that it is necessary to acquire data while OE and CE are low, and to design so that the timings when OE and CE go high do not coincide.
      Is the above recognition correct?

       

      Best Regards

      Arai

        • 1. Re: About tOHC spec for CYUSB3014
          HemanthR_06

          Hi Arai,

           

          When will the data driven from FX3 be sampled by the Master?

           

          I did not fully understand your comment - "Therefore, I understand that it is necessary to acquire data while OE and CE are low, and to design so that the timings when OE and CE go high do not coincide."

          Can you please explain more.

           

          Regards,

          Hemanth

          • 2. Re: About tOHC spec for CYUSB3014
            NoAr_1540581

            Hello  Hemanth san

             

            CYUSB3014 is connected to FPGA, and there is a question about timing when FPGA reads.
            As a premise, tOHC is 0.5ns, and it is a situation where the spec requirement (min.2 ns) of FX3 cannot be satisfied.

            Therefore, they are currently considering how to perform the READ in consideration of the above.
            So please tell us about the following.

            They are examining the situation where tRC, tAA, tAOS, tOH, tOHH, and tOE were observed.This is a method in which the FPGA reads data when OE and CE are Low. OE and CE are kept low for a certain period before and after READ of FPGA. Then, set OE and CE to High.

             

            Q1)
            It is considered that valid data can be obtained if OE and CE are low while keeping tOE. Is it correct?

            Please check the attached.( File name: image.pic17964.gif)


            Also, The timing of tOHC is currently under consideration.

             

            Best Regards

            Arai

             

            • 3. Re: About tOHC spec for CYUSB3014
              HemanthR_06

              Hi Arai,

               

              I don't see any problem if the data is sampled by FPGA  (1) While the OE and CE are low and (2) after waiting for tOE.

              Please do the necessary testing to ensure no issues.

              If possible please post GPIF state machine here so that I can have a look at what actions are being done based on CE.

               

              Regards,

              Hemanth

              • 4. Re: About tOHC spec for CYUSB3014
                NoAr_1540581

                Hello Hemanth san

                 

                Thank you for your reply.

                 

                Best Regards,

                Arai