I tried your program with my CY8CKIT-043.
And the result was High: 9.66ms Low: 10.08ms
Considering that IMO is +/- 2%, not too bad.
But your case, it was about twice longer, so I would imagine that your SysClk was not 48MHz but 24MHz.
Please check the following
(1) Workspace Explorer > Design Wide Resources > Clocks
Double click somewhere blank area of he Clock Tab.
(2) In the "High Frequency Clocks" check if SysClk is 48MHz
If your system does not allow 48MHz, recalculate the number according to the "real" SysClk frequency.
I loaded your project, the same results. Everything is high. I have included two snapshots: the clock page and the logic analyzer.
With your help from before I tried using the PWM blocks with a trigger (perfect). The problem is they drift from the period enough that the duty cycle I have programmed in to the PWM block changes every time I power up the device. I am trying to generate a waveform that is on average 492.5 microseconds. I bumped the SysClk to 48 Mhz and I can not reliably produce on demand this timing.
Is there solution with the PSOC family to generate accurate times in microseconds?
Please and thanks,
From your Clocks table,
IMO 48MHz +/- 2%
ILO 32kHz +/- 6.0%
IMHO, your oscilloscope screen is showing "reasonable" result.
> I am trying to generate a waveform that is on average 492.5 microseconds.
The most important question here is how much deviation you can allow.
If it's +/- 2% current IMO will be fine.
But if you need more accuracy, off my head I can think of the following solutions
(1) Add an external clock or crystal (if the device accept an external crystal) to ExtClk/ECO
(2) Add an 32kHz crystal to wco then trim IMO with it
(3) Use a PSoC with higher accuracy internal clock
In general (1) or (2) is the standard approach, especially if you need high accuracy.
(3) For example 5LP (CY8C5888LTI-LP097) has USB_CLK 48MHz +/- 0.25%
I just received my 5LP prototyping kit, I will be trying this.