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JoBo_4573796
Level 1
Level 1

I am using the PSoC Creator 3.3 and the default notebook project for the CY4541 EX-PD CCG4 Evaluation Kit.  I have a MiniProg3 debugger/programmer.  I can set breakpoint, but is there any way to print statements to a debug console?  The project seems to be ok with including <stdio.h> and printf("Hello World") but will not compile.

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1 Solution

Kindly refer below setting:

pastedImage_0.png

And:

Please kindly recovery back to original setting after the debug is complete and generated product hex file.

Best Regards,

Lisa

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7 Replies
ShifangZ_26
Moderator
Moderator
Moderator
10 likes given 250 sign-ins 1000 replies posted

The way we are recommend is add Software UART TX to debug the firmware.  The recommend way is below:

UART debug for firmware bring up or test.

Open CCGx Project and make sure one of SWD clock / data or other GPIO is available ( using SWD is more convenient, because most design reserve SWD for programming ). Use CCG3PA as example,

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Drag “Software Transmit UART” from component catalog into TopDesign.cysch. And then assigned to SWD_CLK or SWD_DATA.

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Call SW_TX_UART_1_Start() in main.c . Sending “start” is to make sure UART is working.

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NOW, you add anywhere to output the value (Char, string, or others).

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Now you could build the FW and use UART cable ( or USB to Serial cable ) to connect cable_RX (UART_RX) to SWD_Data (UART_TX)

(Cypress USB to Serial kit (CYUSBS232) is can be re-used for USB to UART TX).

You need a software like Tera Term. And then, configure the UART port to receive the data from CCGx.

pastedImage_3.png

Best Regards,

Lisa

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This was close, but did not work on the 2 CY4541 CCG4 kits that I have.  For whatever reason, both kits are off significantly in the baud rate.  In order to get it to work most of the time, I had to set the baud rate of the CCG4 kit to 19200 and the Tera Term baud rate to 14400.  It seems this UART is off for some reason.  When setting at 19200, the baud rate measures on the scope to be 64.2 us/bit instead of 52.1.  When setting at 115200, the baud rate measures on the scope to be 11 us/bit instead of 8.7 us.  By setting the tera term to 14400 (69.4 us/bit), it is close enough to the 64.2 us/bit that the CCG4 kit is generating to work most of the time.

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May I know what's firmware build version on your end? Is the HFCLK in your design is 48MHz and divide from IMO or not?

Best Regards,

Lisa

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The HFCLK is 48 MHz with the source clock of IMO.  I am building with PSoC 3.3 for the CY4541 EX-PD CCG4 Evaluation Kit.  CYPD4225-40LQCI, CCG4, Notebook, Bootloader Base version 0.0.0.58, Firmware version 3.0.0.762.

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Could you please kindly share your project in this thread? So that I could take a look.

Best Regards,

Lisa

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I can share the file.  Where and how do I put it somewhere?

I am able now to get the printf to be generated at the correct baud rate.  I am using PS0C Creator 3.3 and there seems to be an issue in the Generated_Source code.  By temporarily changing the cydelayFreqHz parameter used in the assembly code from 48,000,000 to 40,000,000, it will output the correct baud rate on the SW UART pin.  Below is a copy of the clocks.

pastedImage_0.png

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Kindly refer below setting:

pastedImage_0.png

And:

Please kindly recovery back to original setting after the debug is complete and generated product hex file.

Best Regards,

Lisa

0 Likes