2 Replies Latest reply on Mar 6, 2020 8:57 PM by BoTa_264741

    Representing a 28-bit bus on the PSoC5

    loac_4181281

      I am trying to use a PSoC5 in a project where it will be controlling a chip that uses it's own 28-bit parallel bus. How would I go about representing a non-standard (as in non SPI, I2C, etc.) type of bus on the PSoC5? Do I need to connect each of the 28 lines from the chip to an I/O pin on the PSoC? Has anyone done something like this before? The data sheet for the component I am trying to work with is here: https://ams.com/documents/20143/36005/TDC-GPX_DS000321_1-00.pdf/0b5268df-ea27-b5c6-87cd-e8605aa2c819

       

      Thanks in advance!

        • 1. Re: Representing a 28-bit bus on the PSoC5
          LePo_1062026

          loac,

           

          If the 28-bit data is being latched in the TDC-GPX, then 28-bit parallel access by the PSoC is fairly simple.

           

          Here's a pic of a TopDesign schematic entry using 4 ports (0, 2, 12, and 15) in contiguous mode.

          Here's a pic of the assignment of these ports to ports and pins.

          Here's a code fragment of rading and writing the 28-bit variable in the PSoC.  (Note:  You have to follow the TDC-GPX write/read addressing protocol.)

          uint32 data_28bit;
                  // Read the four ports are one 28-bit value.
                  data_28bit = (Pin_B3_Read()<<24)+ (Pin_B2_Read()<<16) + (Pin_B1_Read()<<8) + Pin_B0_Read();
                  // Write the four ports are one 28-bit value.
                  (Pin_B3_Write((data_28bit>>24)&0xFF)); (Pin_B2_Write((data_28bit>>24)&0xFF)); (Pin_B1_Write((data_28bit>>8)&0xFF)); Pin_B0_Write(data_28bit&0xFF);
          

          If the TDC-GPX doesn't not latch the data, there are some additional circuits needed.

           

          Len

          • 2. Re: Representing a 28-bit bus on the PSoC5
            BoTa_264741

            loac,

            I looked into chip datasheet, and the bus seems to be heterogeneous, so some sections of it can be read independently, for example as 4x8-bit buses, or more buses of smaller size, logically divided among 28 lines. Reading 8-bit bus can be done directly from pins if they are placed continuously (a single port). Smaller buses can be routed to the Status Registers.

            What I am trying to convey here is that reading all 28 lines in a single blob, and then parsing the bits may be the not efficient way of communicating with this chip.

            /odissey1

            PS. Nice chip, BTW. 40 years ago it was whole rack of electronics to accomplish such job.