1 Reply Latest reply on Feb 28, 2020 4:50 AM by AH_96

    SignalNoise Ratio of CapSense - Tolerances of µC?


      Hello all,


      I've got a question about the Signal Noise Ration of the Capsense module.

      In the source code in capsense_processing.c (I'm using the CY8C4024LQI-S411 ), the difference of the raw count and the baseline value is calculated .


      I've checked several of my PCBs (similar PCB layout) and asserted different difference values . Some bad PCBs have a ratio of 57, others 140.

      I have changed the µCs on two boards to exclude the influence of the PCB itself and according the two values of 57 and 140. the lower one got better and the 140 value felt down to 90.


      Does this phenomenon depend on tolerances of different cypress µC?


      Kind regards


        • 1. Re: SignalNoise Ratio of CapSense - Tolerances of µC?

          Hi AnJu_3725101


          It generally does not depend on the tolerance of the controller, assuming the controllers (MPNs) are the same. It does depend on the tuning parameters set in the component.

          If smartsense is set as the tuning option, then some variation is expected between boards in terms of the absolute raw counts/diff counts. Parameters such as resolution might be set differently in both cases causing the issue.


          Please let us know if you are using CapSense tuner to measure the diff counts in both cases. You can also use tuner to measure the SNR directly and as long as the SNR is greater than 5:1, the design is correct.