10 Replies Latest reply on Mar 12, 2020 3:50 AM by LePo_1062026

    PSoC5LP : The trq terminal of DMA componet

    MaMi_1205306

      Hi,

       

      We are using DMA componet of PSoC5LP.

       

      The DMA settings used are as follows:

      (a) Data transfer is individually requested using the drq terminal. (Settings required for each burst)

       

      (b) The source address after data transfer is incremented.

       

      (c) When the transfer of all data specified by the transfer count is completed, loop back to the same TD again.

      (d) Using API of TdSetConfiguration, TD_TERMIN_EN was set to enable the trq pin of the DMA component. (Enable hardware termination)

       

      Under this setting condition, if a positive edge is input to the trq pin after the first burst transfer request,

       

      Is the TD in the state before the first burst request?

      In other words,

      is the transfer count initialized?

      Is the source address pointer initialized?

       

      Regards,

        • 1. Re: PSoC5LP : The trq terminal of DMA componet
          BoTa_264741

          Mami,

          As it is, the question is quite confusing. Maybe it would be better to describe  what you are trying to achieve, or post your project for review.

          /odissey1

          • 2. Re: PSoC5LP : The trq terminal of DMA componet
            MaMi_1205306

            BoTa-san,

             

            I cannot attach a project.

            However, described in red text on the image of the data sheet.

            DMAtrq.JPG

            Would you understand the intent of our question with this image?

             

            Regards,

            • 3. Re: PSoC5LP : The trq terminal of DMA componet
              LePo_1062026

              MaMi,

               

              Please check my understanding of your question.

               

              Operations (a), (b), (c) and (d) appear to work as expected.

              The Question: When a positive-edge pulse on trq is applied, is the TD back in the original state to begin the next transfer?

              For example:

              is the transfer count initialized?

              Is the source address pointer initialized?

              If my understanding is correct, then the answer is "Maybe".

              If the TD is configured as "circular" or "auto-repeat" then it should reset the transfer count and the source address pointer.

              It would depend on how this TD chained.  If it is chained to another TD, it would would initialize the transfer count and source address pointer for that TD.

               

              Here's a snip from the DMA datasheet.

              trq – Input *

              The trq terminal is connected to a component that can terminate a DMA transaction. A component may be asked for data from the DMA when it knows none is available. It uses this signal to terminate the transaction.

              When the current TD in the chain is terminated, it will complete as if the transfer count completed. Therefore, whether the transaction is terminated depends on whether there are other TDs in the chain and what type of transaction is defined (for example, ping-pong, circular, auto-repeat, and so on).

              This signal is only used when the channel is trying to transfer data. A positive edge on this line is ignored at other times.

               

              Len

              • 4. Re: PSoC5LP : The trq terminal of DMA componet
                MaMi_1205306

                Len-san,

                 

                Thank you for your reply.

                 

                Of course, we have already read this data sheet.
                However, the description of the trq terminal is insufficient and cannot be understood.

                 

                Is there anyone who understands correctly, not "Maybe"?

                 

                Regards,

                • 5. Re: PSoC5LP : The trq terminal of DMA componet
                  LePo_1062026

                  MaMi-san,

                   

                  I believe in your case because you wrote:

                  (c) When the transfer of all data specified by the transfer count is completed, loop back to the same TD again.

                  then the answer is "Yes".

                   

                  Are you seeing something different?

                   

                  Len

                  • 6. Re: PSoC5LP : The trq terminal of DMA componet
                    MaMi_1205306

                    Len-san,

                     

                    Sorry for the reconfirmation.

                     

                    /*************************************************************************************************************************/

                    /* 1. Datasheet description */

                    When the current TD in the chain is terminated, it will complete as if the transfer count completed.

                    Therefore, whether the transaction is terminated depends on whether there are other TDs in the chain

                    and what type of transaction is defined (for example, ping-pong, circular, auto-repeat, and so on).

                     

                    /* 2. Our DMA settings */

                    (c) When the transfer of all data specified by the transfer count is completed, loop back to the same TD again.

                     

                    /* 3. Your guess */

                    If the TD is configured as "circular" or "auto-repeat" then it should reset the transfer count and the source address pointer.

                    It would depend on how this TD chained.  If it is chained to another TD, it would would initialize the transfer count and source address pointer for that TD.

                    /*************************************************************************************************************************/

                     

                    In conclusion,
                    When a positive edge is input to the trq of the DMA component,

                    the transfer count is initialized and the source address pointer is initialized.

                     

                    Is the above understanding correct?

                     

                    Regards,

                    • 7. Re: PSoC5LP : The trq terminal of DMA componet
                      LePo_1062026

                      MaMi,

                       

                      Yes.  That is my understanding.

                       

                      Have you seen any different results?

                       

                      Len

                      • 8. Re: PSoC5LP : The trq terminal of DMA componet
                        LePo_1062026

                        To all  monitoring this post,

                         

                        I've created apps using DMA transferred very successfully.  However, I've never had the need to terminate a transfer by CPU or by HW.

                         

                        I created a very simple ping-pong style DMA transfer project to test MaMi's request for information.

                        In this project, the first TD completes in 1 sec and the second TD in 0.5 sec.  It also lights the CY8CKIT059 LED connected to the NRQ output of the DMA component.  Without TD terminates, the LED will blink with a 33% duty cycle.

                         

                        For the HW TRQ I connect the CY8CKIT059's SW1 to a debouncer.  The intent is when I push the SW, the current TD should be terminated.

                        When a TD is asynchronously terminated, I expect the LED blink duty cycle to be temporarily modified.  I couldn't get the HW TRQ to work.  What did I do wrong?

                         

                        The main() for loop has SW commented out that forces a random-ish CPU terminate of the current TD.  When this code is uncommented, it works and terminates the current TD.

                         

                        Attached is the project.  Any ideas what I'm doing wrong with the HW TRQ?

                         

                        MaMi,

                        The SW CPU TD termination does reload the next TD in the chain.  In the ping-pong case of my example project, if TD[0] is terminated, TD[1] is loaded.  If TD[1] is terminated, TD[0] is loaded.   This should also apply to a continuous loop using only one TD.

                         

                        Len

                        • 9. Re: PSoC5LP : The trq terminal of DMA componet
                          EvPa_264126

                          Len, "trq" is active only when transmission is active. therefore it is easier to use an example with DRQ and DMA_REQUEST_PER_BURST = 0

                          I did a small example in this branch, only mixed up the order of the images)))DMA.jpg

                          • 10. Re: PSoC5LP : The trq terminal of DMA componet
                            LePo_1062026

                            Evgeniy,

                             

                            Thanks for the clarification.  Personally I believe the HW trq function is somewhat limited since you MUST be in the middle of a DMA transfer to terminate that TD.  There is very little about the trq in the datasheet.  The only verbage of significance is:

                            trq – Input *

                            The trq terminal is connected to a component that can terminate a DMA transaction. A component may be asked for data from the DMA when it knows none is available. It uses this signal to terminate the transaction.

                            When the current TD in the chain is terminated, it will complete as if the transfer count completed. Therefore, whether the transaction is terminated depends on whether there are other TDs in the chain and what type of transaction is defined (for example, ping-pong, circular, auto-repeat, and so on).

                            This signal is only used when the channel is trying to transfer data. A positive edge on this line is ignored at other times.

                             

                            In a design where the bursts are short, this is a VERY LIMITED window of time where the trq is acted on.

                             

                            However the SW TD terminate forces the termination for the TD whether the transfer is active or not.

                             

                            My opinion,

                             

                            Len