In the current UDB UART component, we can either select one or two stop bits. Its not firmware controlled. The attached project contains modified UART with firmware controlled stop bits.
The verilog was correspondingly modified to take care of this condition. All the modifications in the verilog has been commented with “Keerthi”. So, find this key word for modifications.
bskg-18_2609685_V.rar 5.9 MB
Thank you for attaching the project.
We will run the project and check it.
And we searched for "Keerthi" of keywords but did not find.
Please let us know only the changed part of the UART component.
Because the version of this UART component is old.
We would like to support new UART components.
The modification is in Components -> B_UART_v2_30.v
It is the verilog code of the component. Please check like the following:
If you want to use the latest version component, in Tab-Components, right-click the Project name and select Import Component, then you can import components from project/library and can find v2_50 from CyComponentLibrary. Then do the similar modification in B_UART_v2_50.v
Sorry, we were searching in this Cypress community.
I understood by checking inside the component in PSoC Creator.