I understand that you are trying to implement UVC while the header addition is not done by FPGA and you intend to do it using FX3.
In the firmware which you are using, the UVC headers should be added by the FPGA before transmitting through the slave FIFO interface to the host. Here FX3 is using an Auto DMA channel and hence DMA buffers cannot be modified by CPU.
If you need the FX3 firmware to add the UVC headers, then you will need to use the MANUAL channel for the same - for every buffer sent to the host, the UVC header should be added not just for the frame start and end. Frame end can be detected in the firmware when a DMA call back reports a partial buffer (buffer size should be configured such that for ever resolution you stream the last DMA buffer of a frame is a partial buffer).
CY_U3P_DMA_CB_PROD_EVENT should be monitored in the DMA call back function and when the PROD event occurs, the UVC headers should be added to every producer buffer depending on the buffer size i.e. if its a full buffer or a partial buffer, and then commit the buffer to the consumer i.e. the U-PORT using the CyU3PDmaChannelCommitBuffer() function.
For your reference, I have attached a firmware project which implements UVC with Slave FIFO interface. Please note that the State machine is same as that in AN65974.
You can refer to the CyFxUvcApplnDmaCallback() function in the firmware project for adding the UVC headers for each producer buffer.
UVC_SLaveFifo_Header.zip 2.0 MB