6 Replies Latest reply on Feb 27, 2020 5:29 AM by zeLu_283996

    FX3™ SuperSpeed Explorer Kit can't transfer data bigger than 65536 16bit words

    zeLu_283996

      Hi,

      I'm using CYUSB3KIT-003 EZ-USB® FX3™ SuperSpeed Explorer Kit.

      I connect it with my FPGA board and using asynslavefifo mode. my FPGA board continues to send data  to the Kit by GPIO.  I use either control center or my c++ GUI to receive data from it.The first 65536 16bit words are correct. but after that amount, All the data keep the value of last correct 16bit word.

      for example:   first word:           FC 65

                             second word:     EF 76

       

                              65536th:           F0 19

      then, from now on, all the data change to F0 19, F0 19, F0 19.......

      after an even longer time, all the data changed to 00 00, 00 00,......

       

      I tried either small frame(everytime transfer in a small amout of bytes like 1024, 4096 or 8192 ... but frame by frame continuously), or big frame(like 65536 , 131 072 or even bigger).

      The result is the same.

       

      in the firmware, DMA transfer size is set to infinite:

      #define CY_FX_SLFIFO_DMA_TX_SIZE        (0)                   /* DMA transfer size is set to infinite */

      #define CY_FX_SLFIFO_DMA_RX_SIZE        (0)                   /* DMA transfer size is set to infinite */

       

      any one can help?

       

      Thank

       

      Zen

        • 1. Re: FX3™ SuperSpeed Explorer Kit can't transfer data bigger than 65536 16bit words
          JayakrishnaT_76

          Hello,

           

          Please let me know the following details:

          1. Which firmware are you using for this project? Is it the one provided along with FX3 SDK? Or have you changed anything?

          2. What is the size of the DMA Buffer from P Port to U Port?

          3. Please confirm that the 65537th 16 bit word transmitted by FPGA is not F0 19 regardless of the frame size.

          4. Please let me know which FPGA you are using.

           

          Also in your query, you mentioned that "I tried either small frame(everytime transfer in a small amount of bytes like 1024, 4096 or 8192 ... but frame by frame continuously), or big frame(like 65536 , 131 072 or even bigger). The same result is the same."

          According to my understanding, even when you tried to split data into 1024, 4096 or 8192, you were able to see the same result. That is from 65537th word, the data is same as that of the 65536th word. When you tried to transfer 131072 bytes or even bigger data also, from the 65537th word, the data was same as that of 65536th word. Please correct me if Iam wrong.

           

          Best Regards,

          Jayakrishna

          • 2. Re: FX3™ SuperSpeed Explorer Kit can't transfer data bigger than 65536 16bit words
            zeLu_283996

            Hi, Jayakrishna:

             

            Thank you very much.

             

            about the details you asked for:

            1. the firmware is the one from EZ-USB FX3 SDK/1.3/firmware/slavefifi_examples/slavefifoasync.  I just tried change the

            #define CY_FX_SLFIFO_DMA_BUF_COUNT      (2)  to #define CY_FX_SLFIFO_DMA_BUF_COUNT      (8)

            and rebuilt it  only. the difference is the max size changed from 131072 to 65536.

            2. I don't know where to set P2U port buffer, just see the tx and rx buffer already set to infinite. because I didn't do any change, it should be as it is. please help me check where and how to change.

            3. F0 19 is just an example, it may be any value depends on what the FPGA transfered to it, the following eaxmple shows 0A 08.the first block is what I needed, the second block is the repeat of last 0A 08.

            the figure below is the result after click 9 times for bytes to transfer set as 8192

             

             

            4. The FPGA I used is Cyclone V. my product works fine with FX2, and I want to upgrade to FX3.

             

            on the bottom, your understanding is exactly correct.

            • 3. Re: FX3™ SuperSpeed Explorer Kit can't transfer data bigger than 65536 16bit words
              JayakrishnaT_76

              Hello,

               

              Please find the attached state machine for asynchronous slave FIFO interface using 2 bit addressing mode.

              The control signals pkend, slcs and slwr are used for writing into the the DMA Buffers in P Port. When both slcs and slwr are low, the data available on the data bus (coming from FPGA) is sampled. When SLWR is de-asserted (goes high), the sampled data is stored in the data sink. Again, when SLWR is re-asserted, data is sampled and this is repeated until PKEND is asserted (goes low) where the SHORT_PKT is committed.

               

              According to this state machine, FX3 will sample the data which comes from the FPGA when the control signals are asserted. As you are able to get first 65536 bytes properly and from there, the data is repeating, please check the data that is provided by FPGA to FX3 after the 65536th byte. Please probe the data bus after sending 65536 bytes and share it with us so that we can understand the same.

               

              Best Regards,

              Jayakrishna 

              • 4. Re: FX3™ SuperSpeed Explorer Kit can't transfer data bigger than 65536 16bit words
                zeLu_283996

                Hi, Jayakrishna;

                Thank you for your reply.

                 

                you mentioned P to U port buffer before, please help me to find where can I change its buffer size and buffer count.

                on some examples, they have some suggestions like:

                "

                The DMA channels described in this section are set up if the following define is enabled in the cyfxslfifosync.h file

                in the FX3 firmware project provided with this application note.

                /* set up DMA channel for stream IN/OUT transfers */

                #define STREAM_IN_OUT

                The buffer count allocated to the P2U and U2P DMA channels can be controlled by using the following defines,

                also present in the cyfxslfifosync.h file:

                /* Slave FIFO P_2_U channel buffer count */

                #define CY_FX_SLFIFO_DMA_BUF_COUNT_P_2_U (4)

                /* Slave FIFO U_2_P channel buffer count */

                #define CY_FX_SLFIFO_DMA_BUF_COUNT_U_2_P (8)

                "

                but I can't find where this section is located.

                Can I simply add the following in the cyfxslfifoasync.h file?

                #define STREAM_IN_OUT

                /* Slave FIFO P_2_U channel buffer count */

                #define CY_FX_SLFIFO_DMA_BUF_COUNT_P_2_U (8)

                /* Slave FIFO U_2_P channel buffer count */

                #define CY_FX_SLFIFO_DMA_BUF_COUNT_U_2_P (4)

                 

                 

                 

                appreciate

                 

                Zen

                • 5. Re: FX3™ SuperSpeed Explorer Kit can't transfer data bigger than 65536 16bit words
                  JayakrishnaT_76

                  Hello Zen,

                   

                  Please find the snippet below which contains the code for creation of DMA channel from U Port to P Port and from P Port to U Port.

                   

                   

                  This can be found in the file cyfxslfifoasync.c file. Here,

                   

                  The dmaCfg.size gives the buffer size associated with the DMA channel. Note that size is same for both the channels here.

                  The dmaCfg.count gives the number of such buffers that are allocated to the DMA channel. This is also same for both the channels.

                   

                  According to the code, currently the size of the DMA buffer is set based on the USB speed. That is it is 64 bytes for Full Speed, 512 for High Speed and 1024 for super speed. You can try varying the DMA buffer size. As you might be knowing that this example project makes use of default memory mapping for the 512 KB SRAM. That is, only 224 KB out of the available 512 KB SRAM of FX3 can be used for the creation of DMA Buffers. Out of this, some amount of memory is used for the creation of Control channel and UART debug channel. So, to be on the safe side, ensure that the total size of DMA buffers allocated is less than 218 KB. If this is not met, then the device will not enumerate. So when you are increasing the DMA Buffer size, if the total size of allocated DMA buffers for both the channels go beyond 218 KB, please reduce the number of buffers or the size of DMA buffer.

                   

                  Best Regards,

                  Jayakrishna