6 Replies Latest reply on Mar 10, 2020 8:40 PM by yuxi_3250341

    S29JL064H Timing error: tGHVL hold violatin

    yuxi_3250341

      Hi there,

      While I am using Cypress S29JL064H Verilog simulation model to do behavioral simulation, the sim log gives a weird timing Error:

        # ** Error: ../vrf/S29jl064h/model/s29jl064h.v(1161): $hold( posedge OENeg:1000951 ns, CENeg:1000951 ns, 1 ns );

        #    Time: 1000951 ns  Iteration: 1  Instance: /tb_norc/U_064H

      Follow this error, line 1161 in <s29jl064h.v> is:

        $hold (posedge OENeg, CENeg , thold_WENeg_OENeg, Viol);

      And, the comments of "thold_WENeg_OENeg" says "tGHVL edge /".

       

      In my simulation waveform, at the specified time (1000951 ns), the OE# rising edge and OE# rising occurs at exactly the same time. However, it seems the $hold requirement in the model requires that CE# rising edge should be later than posedge OE#, and seems this is defined by "tGHVL" parameter.

      I went through the datasheets of S29JL064H, S29JL064J, S29GL256P and S29GL01GT, and there is NOT such an AC parameter called "tGHVL", and I CANNOT find any spec requiring that CE# rising edge should be later than posedge OE#.

       

      Where can I find the definition of "tGHVL"?

      Can I ignore the forthmentioned timing Error issued by the S29JL064H Verilog simulation model?

      Or, should I modify my design to ensure that no timing error is reported?