Hello KeDa_1385231 ,
For a UDB counter in Down Counter or Up Counter clock mode the edge detect logic detects the rising edge of the count input synchronous to the clock input. Depending on whether the Counter is configured as an up counter or down counter, the edge detect event on the count input increments or decrements the Counter, respectively
The terminal count condition is met in case of down counter when counter value is equal to zero.
Thus you need should not provide logic high to the count input of the counter
Use the following method to provide input to the count terminal:
I am attaching a project with one shot counter implementation as mentioned by you, please try it on the development board.
You will notice LED blink when the terminal count is reached.
TC_Counter.cyprj.Archive01.zip 499.9 K
Attached is demo project: quadrature pulse train generator. It uses custom component ClockN, which generates train of clock pulses; each 4 clock pulses produce a single IQ pair. Project uses clock Timer to re-trigger ClockN generator at approx 125Hz rate. Quadrature frequency is controlled by Clock_1.
Project tested using CY8CKIT-059 Prototyping Kit. All custom components are included into the project.
As I think the "count" input of the counter is "edge" triggered,
I modified your schematic like below
Note: I used CY8CKIT-059
CyGlobalIntEnable; /* Enable global interrupts. */
The oscilloscope output was
I also measured GEN_CLK and it was generating about 200kHz.
And yes, tc is asserted this time.
So the good news is it seems to be working.
The bad news is as I'm not familar with quad... I don't know if this is what you wanted.