5 Replies Latest reply on Mar 2, 2020 6:47 PM by ShifangZ_26

    CCG3PA: Missing "GOOD CRC" ACK Response

    NaWo_4517846

      I've got a CYPD3171-24LQXQ that I'm attempting to get working as an UFP (sink) and am having trouble even getting essentially the stock Power Bank demo to successfully negotiate a power contract.

       

      Unfortunately I'm not seeing the CCG3PA device respond with any "GOOD CRC" acknowledgement messages to the source capabilities messages. The source trys a few times, eventually sending a Hard Reset request, looping through this process a few times, and finally giving up. Here are some oscilloscope and logic analyzer captures of the series of events:
      Full Stream - Annotated.png 

      Full Stream - Logic Analyzer.png

      A slightly more detailed view of the first set of events up until the Hard Reset request:

      Detailed Start Annotated.png

      Detailed Start - Logic Analyzer.png

      An even more detailed view of the "source capabilities" event (they're all identical):Source Capabilities - Logic Analyzer.png
      And finally, a detail view of the Hard Reset packet:

      Hard Reset - Logic Analyzer.png

       

      I've also added some UART logging of the following:

      • APP_VBUS_SNK_FET_ON_P1
      • APP_VBUS_SRC_FET_OFF_P1
      • APP_SINK_SET_CURRENT_P1
      • APP_VBUS_SET_VOLT_P1
      • All "app_event_handler" events
      • Device bootup

       

      <<<<<<<<<<< Device Powered On
      
      (18:08:34.617) (0.000) BOOT
      (18:08:35.852) (1.234) APP_VBUS_SNK_FET_OFF_P1
      (18:08:35.852) (0.000) PD port enable (start) completed.
      
      <<<<<<<<<<< Plugged in
      
      (18:09:28.603) (52.751) Type-C AttachWait state entered. For internal use only.
      (18:09:28.865) (0.261) Type-C attach event.
      (18:09:28.865) (0.000) APP_SINK_SET_CURRENT_P1(3000,5000)
      (18:09:28.865) (0.000) APP_VBUS_SNK_FET_ON_P1
      (18:09:28.865) (0.000) Type-C connect.
      (18:09:29.263) (0.398) Hard Reset sent by CCG.
      (18:09:29.263) (0.000) APP_VBUS_SET_VOLT_P1(5000)
      (18:09:29.263) (0.000) APP_VBUS_SRC_FET_OFF_P1
      (18:09:29.263) (0.000) APP_VBUS_SNK_FET_OFF_P1
      (18:09:30.184) (0.921) Hard Reset processing completed.
      (18:09:30.184) (0.000) APP_SINK_SET_CURRENT_P1(3000,5000)
      (18:09:30.184) (0.000) APP_VBUS_SNK_FET_ON_P1
      (18:09:30.583) (0.398) Hard Reset sent by CCG.
      (18:09:30.583) (0.000) APP_VBUS_SET_VOLT_P1(5000)
      (18:09:30.583) (0.000) APP_VBUS_SRC_FET_OFF_P1
      (18:09:30.583) (0.000) APP_VBUS_SNK_FET_OFF_P1
      (18:09:31.503) (0.920) Hard Reset processing completed.
      (18:09:31.503) (0.000) APP_SINK_SET_CURRENT_P1(3000,5000)
      (18:09:31.503) (0.000) APP_VBUS_SNK_FET_ON_P1
      (18:09:31.903) (0.399) Hard Reset sent by CCG.
      (18:09:31.903) (0.000) APP_VBUS_SET_VOLT_P1(5000)
      (18:09:31.903) (0.000) APP_VBUS_SRC_FET_OFF_P1
      (18:09:31.903) (0.000) APP_VBUS_SNK_FET_OFF_P1
      (18:09:32.824) (0.921) Hard Reset processing completed.
      (18:09:32.824) (0.000) APP_SINK_SET_CURRENT_P1(3000,5000)
      (18:09:32.824) (0.000) APP_VBUS_SNK_FET_ON_P1
      (18:09:33.209) (0.384) PE.Disabled state entered.
      (18:09:37.777) (4.568) APP_VBUS_SNK_FET_OFF_P1
      (18:09:37.777) (0.000) Type-C disconnect(detach).
      (18:09:37.777) (0.000) Type-C AttachWait state entered. For internal use only.
      (18:09:38.657) (0.879) Type-C attach event.
      (18:09:38.657) (0.000) APP_SINK_SET_CURRENT_P1(3000,5000)
      (18:09:38.673) (0.015) APP_VBUS_SNK_FET_ON_P1
      (18:09:38.673) (0.000) Type-C connect.
      (18:09:39.072) (0.399) Hard Reset sent by CCG.
      (18:09:39.072) (0.000) APP_VBUS_SRC_FET_OFF_P1
      (18:09:39.072) (0.000) APP_VBUS_SRC_FET_OFF_P1
      (18:09:39.072) (0.000) APP_VBUS_SNK_FET_OFF_P1
      (18:09:39.994) (0.921) Hard Reset processing completed.
      (18:09:39.994) (0.000) APP_SINK_SET_CURRENT_P1(3000,5000)
      (18:09:39.994) (0.000) APP_VBUS_SNK_FET_ON_P1
      (18:09:40.393) (0.398) Hard Reset sent by CCG.
      (18:09:40.393) (0.000) APP_VBUS_SET_VOLT_P1(5000)
      (18:09:40.393) (0.000) APP_VBUS_SRC_FET_OFF_P1
      (18:09:40.393) (0.000) APP_VBUS_SNK_FET_OFF_P1
      (18:09:41.313) (0.920) Hard Reset processing completed.
      (18:09:41.313) (0.000) APP_SINK_SET_CURRENT_P1(3000,5000)
      (18:09:41.313) (0.000) APP_VBUS_SNK_FET_ON_P1
      (18:09:41.712) (0.398) Hard Reset sent by CCG.
      (18:09:41.712) (0.000) APP_VBUS_SET_VOLT_P1(5000)
      (18:09:41.712) (0.000) APP_VBUS_SRC_FET_OFF_P1
      (18:09:41.712) (0.000) APP_VBUS_SNK_FET_OFF_P1
      (18:09:42.634) (0.922) Hard Reset processing completed.
      (18:09:42.634) (0.000) APP_SINK_SET_CURRENT_P1(3000,5000)
      (18:09:42.634) (0.000) APP_VBUS_SNK_FET_ON_P1
      (18:09:43.018) (0.383) PE.Disabled state entered.
      (18:09:47.586) (4.568) APP_VBUS_SNK_FET_OFF_P1
      (18:09:47.586) (0.000) Type-C disconnect(detach).
      (18:09:47.586) (0.000) Type-C AttachWait state entered. For internal use only.
      (18:09:48.467) (0.880) Type-C attach event.
      (18:09:48.467) (0.000) APP_SINK_SET_CURRENT_P1(3000,5000)
      (18:09:48.483) (0.015) APP_VBUS_SNK_FET_ON_P1
      (18:09:48.483) (0.000) Type-C connect.
      (18:09:48.881) (0.398) Hard Reset sent by CCG.
      (18:09:48.881) (0.000) APP_VBUS_SET_VOLT_P1(5000)
      (18:09:48.881) (0.000) APP_VBUS_SRC_FET_OFF_P1
      (18:09:48.881) (0.000) APP_VBUS_SNK_FET_OFF_P1
      (18:09:49.802) (0.920) Hard Reset processing completed.
      (18:09:49.802) (0.000) APP_SINK_SET_CURRENT_P1(3000,5000)
      (18:09:49.802) (0.000) APP_VBUS_SNK_FET_ON_P1
      (18:09:50.202) (0.399) Hard Reset sent by CCG.
      (18:09:50.202) (0.000) APP_VBUS_SRC_FET_OFF_P1
      (18:09:50.202) (0.000) APP_VBUS_SRC_FET_OFF_P1
      (18:09:50.202) (0.000) APP_VBUS_SNK_FET_OFF_P1
      (18:09:51.123) (0.921) Hard Reset processing completed.
      (18:09:51.123) (0.000) APP_SINK_SET_CURRENT_P1(3000,5000)
      (18:09:51.123) (0.000) APP_VBUS_SNK_FET_ON_P1
      (18:09:51.522) (0.398) Hard Reset sent by CCG.
      (18:09:51.522) (0.000) APP_VBUS_SET_VOLT_P1(5000)
      (18:09:51.522) (0.000) APP_VBUS_SRC_FET_OFF_P1
      (18:09:51.522) (0.000) APP_VBUS_SNK_FET_OFF_P1
      (18:09:52.442) (0.920) Hard Reset processing completed.
      (18:09:52.442) (0.000) APP_SINK_SET_CURRENT_P1(3000,5000)
      (18:09:52.442) (0.000) APP_VBUS_SNK_FET_ON_P1
      (18:09:52.826) (0.383) PE.Disabled state entered.
      (18:09:57.395) (4.569) APP_VBUS_SNK_FET_OFF_P1
      (18:09:57.395) (0.000) Type-C disconnect(detach).
      (18:09:57.395) (0.000) Type-C AttachWait state entered. For internal use only.
      (18:09:58.275) (0.879) Type-C attach event.
      (18:09:58.275) (0.000) APP_SINK_SET_CURRENT_P1(3000,5000)
      (18:09:58.292) (0.016) APP_VBUS_SNK_FET_ON_P1
      (18:09:58.292) (0.000) Type-C connect.
      (18:09:58.689) (0.397) Hard Reset sent by CCG.
      (18:09:58.689) (0.000) APP_VBUS_SET_VOLT_P1(5000)
      (18:09:58.689) (0.000) APP_VBUS_SRC_FET_OFF_P1
      (18:09:58.689) (0.000) APP_VBUS_SNK_FET_OFF_P1
      (18:09:59.611) (0.921) Hard Reset processing completed.
      (18:09:59.611) (0.000) APP_SINK_SET_CURRENT_P1(3000,5000)
      (18:09:59.611) (0.000) APP_VBUS_SNK_FET_ON_P1
      (18:10:00.009) (0.398) Hard Reset sent by CCG.
      (18:10:00.009) (0.000) APP_VBUS_SRC_FET_OFF_P1
      (18:10:00.009) (0.000) APP_VBUS_SRC_FET_OFF_P1
      (18:10:00.009) (0.000) APP_VBUS_SNK_FET_OFF_P1
      (18:10:00.931) (0.921) Hard Reset processing completed.
      (18:10:00.931) (0.000) APP_SINK_SET_CURRENT_P1(3000,5000)
      (18:10:00.931) (0.000) APP_VBUS_SNK_FET_ON_P1
      (18:10:01.331) (0.399) Hard Reset sent by CCG.
      (18:10:01.331) (0.000) APP_VBUS_SET_VOLT_P1(5000)
      (18:10:01.331) (0.000) APP_VBUS_SRC_FET_OFF_P1
      (18:10:01.331) (0.000) APP_VBUS_SNK_FET_OFF_P1
      (18:10:02.251) (0.920) Hard Reset processing completed.
      (18:10:02.251) (0.000) APP_SINK_SET_CURRENT_P1(3000,5000)
      (18:10:02.251) (0.000) APP_VBUS_SNK_FET_ON_P1
      (18:10:02.635) (0.383) PE.Disabled state entered.
      (18:10:08.777) (6.142) Rp termination change.
      
      <<<<<<<<< SOURCE STOPS ATTEMPTING NEGOTIATION
      
      <<<<<<<<<< UNPLUGGED
      
      (18:10:35.746) (26.969) APP_VBUS_SNK_FET_OFF_P1
      (18:10:35.746) (0.000) Type-C disconnect(detach).
      (18:10:35.767) (0.021) Type-C AttachWait state entered. For internal use only.
      (18:10:36.036) (0.268) Type-C transition from AttachWait to Unattached. For internal use only.
      

       

       

      From a hardware perspective, I've stripped down to disabling the Type-A port, and only have the following connected:

      • CC1(decoupled to GND via 390pF capacitor)
      • CC2 (decoupled to GND via 390pF capacitor)
      • GND
      • VCCD (decoupled to GND via 1uF capacitor)
      • VDD (+5V from an external regulator, decoupled to ground via a 0.1 uF capacitor)
      • CSP (connected to ground via a 5mOhm current sense resistor)
      • VBUS_IN_DISCHARGE (connected straight to VBUS without any provider of consumer FETs, the application does not require this protection )
      • UART TX to an external USB->UART device for debugging

      (I've attached an export of my PSoC Creator Project "noboot.cyprj.Archive01.zip")

       

      In the EZ-PD Configuration Utility, I've set the following

      • Sink only (UFP)
      • Disabled OVP, OCP, UVP, SCP, and OTP
      • Two PDO's
        • Fixed Supply: 5V
        • Variable Supply: 5-20V

      (I've attached the output files from this configuration "EZ-PD Config Settings.zip")

       

       

      Is there something I might be missing here? It sure seems like the Source device is correctly detecting the UFP resistors, and the CCG3PA is getting "Attach", "Connect", and "Hard Reset" events firing all the way up to the application layer, so I don't think I've got a hardware problem. But, this prototype device was hand assembled.. so proper reflow is always a potential suspect, but I'd think I would be seeing indicators of problems elsewhere if this were the case (or CC1 vs. CC2 behaving differently).

       

      Thanks for any insight you may be able to provide


      Kind Regards,
      Nathan W.

        • 1. Re: CCG3PA: Missing "GOOD CRC" ACK Response
          ShifangZ_26

          Hi Nathan,

           

          1. May I know whether you have CC snifer tool can catch the CC log on the CC line or not? If yes, could you please share it in this thread?

          >> Cypress have CY4500 for CC log sniffer. If you are using CY4500, please kindly share .ccgx format.

           

          2. The configuration file and the behavior shows above is mismatched. As you can see, the UART you supplied is requesting 5V3A as per the log you supplied. And the config you attached is 5V/900mA for PDO0, and 5-20V/900mA for PDO1.

           

          3, What's example firmware you are based on? If you are using CYPD3171-24LQXQ_pb, please set POWER_BANK as 0 in file config.h.

          #define POWER_BANK                                  (0)

           

          4. Could you please test the firmware you have been changed on the CY4532 and make sure the issue can be reproduced?

           

          Best Regards,

          Lisa

          • 2. Re: CCG3PA: Missing "GOOD CRC" ACK Response
            NaWo_4517846

            1) Nope, I don't have the CY4500 available to me, but I'm confident in my 3rd party logic analyzer's readings. I can view other UFP products (my phone) correctly transacting

             

            2) I agree!

             

            3) Yes, I'm using the PB firmware. After setting POWER_BANK to 0, I get a similar behavior (physically) but a slightly different log response:

            (20:01:25.058) (0.000) (>>) œ<NUL><NUL><NUL>BOOT<LF>

            (20:01:25.685) (0.626) (>>) APP_VBUS_SNK_FET_OFF_P1<LF>

            (20:01:25.685) (0.000) (>>) PD port enable (start) completed.<LF>

            (20:01:31.716) (6.031) (>>) Type-C AttachWait state entered. For internal use only.<LF>

            (20:01:31.972) (0.255) (>>) Type-C attach event.<LF>

            (20:01:31.972) (0.000) (>>) APP_VBUS_SNK_FET_ON_P1<LF>

            (20:01:31.972) (0.000) (>>) Type-C connect.<LF>

            (20:01:32.384) (0.412) (>>) Hard Reset sent by CCG.<LF>

            (20:01:32.384) (0.000) (>>) APP_VBUS_SET_VOLT_P1(5000)<LF>

            (20:01:32.384) (0.000) (>>) APP_VBUS_SRC_FET_OFF_P1<LF>

            (20:01:32.384) (0.000) (>>) APP_VBUS_SNK_FET_OFF_P1<LF>

            (20:01:33.119) (0.735) (>>) Hard Reset processing completed.<LF>

            (20:01:33.119) (0.000) (>>) APP_VBUS_SNK_FET_ON_P1<LF>

            (20:01:33.503) (0.383) (>>) Hard Reset sent by CCG.<LF>

            (20:01:33.525) (0.021) (>>) APP_VBUS_SET_VOLT_P1(5000)<LF>

            (20:01:33.525) (0.000) (>>) APP_VBUS_SRC_FET_OFF_P1<LF>

            (20:01:33.525) (0.000) (>>) APP_VBUS_SNK_FET_OFF_P1<LF>

            (20:01:34.244) (0.719) (>>) Hard Reset processing completed.<LF>

            (20:01:34.263) (0.018) (>>) APP_VBUS_SNK_FET_ON_P1<LF>

            (20:01:34.643) (0.380) (>>) Hard Reset sent by CCG.<LF>

            (20:01:34.643) (0.000) (>>) APP_VBUS_SET_VOLT_P1(5000)<LF>

            (20:01:34.676) (0.032) (>>) APP_VBUS_SRC_FET_OFF_P1<LF>

            (20:01:34.676) (0.000) (>>) APP_VBUS_SNK_FET_OFF_P1<LF>

            (20:01:35.396) (0.719) (>>) Hard Reset processing completed.<LF>

            (20:01:35.396) (0.000) (>>) APP_VBUS_SNK_FET_ON_P1<LF>

            (20:01:35.779) (0.383) (>>) PE.Disabled state entered.<LF>

            (20:01:59.645) (23.865) (>>) Rp termination change.<LF>

            (20:10:29.830) (8:30.185) (>>) APP_VBUS_SNK_FET_OFF_P1<LF>

            (20:10:29.830) (0.000) (>>) Type-C disconnect(detach).<LF>

            (20:10:29.830) (0.000) (>>) Type-C AttachWait state entered. For internal use only.<LF>

            4) I was hoping to avoid a CY4532, as it targets a much more complex application than our goals... but I've got one on order and will update this thread with my results.

             

             

            Perhaps I can reword things for a more direct question: What are the minimum requirements from both a hardware and firmware modification perspective to get the CYPD3171-24LQXQ acting as an UFP?

            • 3. Re: CCG3PA: Missing "GOOD CRC" ACK Response
              ShifangZ_26

              Since you are not have CY4532, could you please share the schematic you are testing to me? So that I can take a look if there is any hardware design not following default firmware?

              • 4. Re: CCG3PA: Missing "GOOD CRC" ACK Response
                NaWo_4517846

                I have now purchased a CY4532 and have been able to pair the PB firmware down enough to run the "Main Board" as a stand alone UFP (without the power board attached at all), only requiring a jumper between RETURN_GND and GND, additionally all jumpers have been removed other than J4 in position 23. I believe this functionally looks something like the following schematic. I've removed any "no load" components along with and jumper paths that would now be unused. Everything is working as expected here.

                Then moving over to my prototype board I've got the following, what a believe to be the minimum requirements to act as a UFP. Using the same firmware as on the dev-kit I'm experiencing the same results in my original post.

                • 5. Re: CCG3PA: Missing "GOOD CRC" ACK Response
                  ShifangZ_26

                  Could you please share VBUS, CC1, CC2 waveform in this thread?

                   

                  Best Regards,

                  Lisa