3 Replies Latest reply on Feb 17, 2020 4:17 AM by YatheeshK_36

    How to avoid or reduce Salve FIFO full flags?


      Dear Sirs,

      We need to send the Realtime data from Slave FIFO master in a few uS, but USB transmission always results into the asserted Full flags. Then Slave FIFO Master would report timeout! What’s wrong about the FIFO full flags! It always lasts thousands of uS, or Oven a few mS. That would be a very very slow speed transmission. How should we do about this? We have test with Bulk & Isochronous mode.

      Is there any method to avoid or reduce Salve FIFO full flags?

      And in the Spec, the time of flags lasting is not illustrated. Could you explain this time for me!

      Thanks a lot!

      Waiting for your Reply!

        • 1. Re: How to avoid or reduce Salve FIFO full flags?



          When FX2LP is configured in Slave FIFO mode, the full flags will be asserted till the corresponding FIFO is full.


          Please see the methods below:


          1. One way you can de-assert the Full flag is to continuously monitor the FIFO flag and empty the FIFO either by committing the data to the endpoint buffer or by discarding the FIFO data (which will result in data loss) so that the full-flag will be de-asseted.

          You can continuously commit the FIFO data to the endpoint buffer in AUTO Mode using AUTOIN method, where the FIFO once filled will get automatically committed to the end-point buffer. In this case, you can use the steamer application to continuously stream-in the real time data from the FX2LP.


          2. You can also reduce the rate a which the data is sent and sampled by reducing the interface clock frequency between the FX2LP slave and the FIFO master.


          3. Increasing the endpoint buffer size to maximum 1024 will allow more data to be filled hence increasing the interval where the FIFO will be filled completely.


          4. To avoid full flag, you can leave it unconnected from the FX2LP end and de-assert (pulled high/low) on the FPGA end, in this case the FPGA thinks that the FX2LP FIFO always has a place to store data and keeps writing to it, but in this case the written data after the FIFO is actually Full is lost.


          Please let me know if any of the above methods will solve your issue.

          If not, can you please let me know the interface frequency,  and the firmware you are using for your application?

          You can also share your firmware.


          Best Regards,


          • 2. Re: How to avoid or reduce Salve FIFO full flags?

            Thanks for your reply!

            Now it is confusing when the full flag would be asserted.

            For exampe, we set the EP6 FIFO as Buffer size =512 , x4, and Wordwide=1,AUTOINLEN = 0x200, MaxPktSize = 0x200.

            And when would the full flag be asserted? Write 512 bytes? or 2048 bytes?

            then if we setting AUTOINLEN = 0x100, then How much bytes would one packet contain?

            • 3. Re: How to avoid or reduce Salve FIFO full flags?



              In this case, the FIFO full flag will be asserted when there are no free FIFO buffers to fill i.e. 2048 bytes are completely filled in FIFO and none of the buffers are committed and read from the host side. Full flag will be asserted only when all the buffers are completely filled.


              You can use EP2 where buffer size is configured as 1024 and quad/triple buffered, in that case the full flag will be asserted after completely filling all three/four FIFO buffers which gives more time for the the FIFO Master to fill data.


              If AUTOINLEN of an endpoint is 0x100 then the buffer will be committed to the endpoint (SIE) after the buffer has 256 bytes of data as a 256 bytes packet.

              Please assign AUTOINLEN with a value equal to the maximum packet size that is advertised to the host for maximum throughput, if the maximum packet size is 512 then AUTOINLEN = 0x200 and for 1024, AUTOINLEN = 0x400.