10 Replies Latest reply on Feb 25, 2020 7:16 PM by ShupingZ_76

    FRAM : FM24C16B-G : Software reset

    MaMi_1205306

      Hi,

       

      While accessing this FRAM of I2C interface, the CPU may be reset.
      When the CPU accesses FRAM after returning from reset, FRAM cannot output data normally.

      This FRAM only has a power-on reset and no external reset.

      Does FM24C16B-G have a software reset?

       

      For example, MB85RC16V(Fujitsu) has the following description.

      It seems that software reset is performed by sending 9 times clock to FRAM.
      Is this function effective for FM24C16B-G?

       

      Regards,

        • 1. Re: FRAM : FM24C16B-G : Software reset
          ShupingZ_76

          Hi,

          FM24C16B-G doesn't have the software reset function.

           

          Regards,

          • 2. Re: FRAM : FM24C16B-G : Software reset
            MaMi_1205306

            Thank you for your support.

             

            That is, the device has no hard or soft reset.

            Do you know how to avoid resetting while the CPU is reading FRAM data?

             

            Is it only a means for the CPU after reset release to output an arbitrary number of clocks and wait for an ACK / NACK response?

             

            Regards,

            • 3. Re: FRAM : FM24C16B-G : Software reset
              ShupingZ_76

              In my understanding, a stable power supply could keep the device stable.

               

              After the CPU reset, CPU should follow the I2C interface standard to access the I2C device.

               

              Please let me know if I made any misunderstanding on your questions.

              • 4. Re: FRAM : FM24C16B-G : Software reset
                MaMi_1205306

                Hi,

                 

                1. CPU performs read access to I2C FRAM

                2. CPU resets while accessing I2C FRAM.

                3. While the CPU is reset, the I2C IF of the CPU is Hi-Z.

                4. Sometimes SDA keeps 'L' output state

                5. If SDA does not become 'H', it will not start condition

                6. CPU returns from reset

                 

                Even if the CPU is reset at 4.7V, the FRAM will not fall below the lower limit of 4.5V and will not become a POR.

                 

                 

                After the CPU returns from reset,

                Accessing I2C FRAM is not a start condition,

                As a FRAM, it only looks like the L period of the I2C SCL is long.

                Data cannot be obtained normally.

                 

                A hard reset terminal is, of course, not provided for this device.

                I think a soft reset is necessary to avoid this situation.

                Or the only way to generate the I2C CLK that has been stopped during access so that the data can be acquired normally.

                Please provide us if there is the best workaround.

                 

                Regard,

                 

                • 5. Re: FRAM : FM24C16B-G : Software reset
                  MaMi_1205306

                  FM24C16B-G : SCL tLOW characteristics

                   

                  We have obtained the following answer from a previous question:

                  "Even if the 'L' period of CLK is long, data can be acquired normally."

                  In fact, this long L period of 20us,
                  The CPU enters the reset state, and after returning, starts accessing the I2C FRAM.

                  The CPU enters the reset state while issuing the command.
                  After reset, the CPU issues a new command.
                  Obviously, data different from the intended data is obtained.

                  This problem must be avoided.

                  • 6. Re: FRAM : FM24C16B-G : Software reset
                    ShupingZ_76

                    Thank you very much for your explanation.

                    When the CPU reset, the operation in progress should be aborted and re-execute.

                    As mentioned in "START Condition (S)" in the datasheet, an operation in progress can be aborted by asserting a START condition at anytime. Aborting an operation using the START condition will ready the FM24C16B for a new operation.

                    I hope this could address your inquiry.

                    • 7. Re: FRAM : FM24C16B-G : Software reset
                      MaMi_1205306

                      Hi,

                       

                      Sorry to confirm  again and again.

                       

                      Please look at the waveform below.]

                      Since FRAM is in the middle of 8-bit data reading, 'L' is output for SDA.

                      Described in the data sheet,
                      The bus master cannot drive SDA from HIGH to LOW when the SCL signal is HIGH.
                      That is, the bus master cannot generate a start condition.

                       

                      Regards,

                      • 8. Re: FRAM : FM24C16B-G : Software reset
                        ShupingZ_76

                        If FRAM is in the middle of 8-bit data reading, 'L' is output for SDA, after the CPU reset, the CPU needs to issue a min of 8 dummy clocks so that FRAM completes its ongoing byte read and releases the bus.

                         

                        Following is a recommend sequence for CPU to "reset" I2C FRAM after CPU reset:

                        1. Send “Start” (This "Start" may be rejected by FRAM if FRAM is holding SDA to logic low, but it doesn't matter)

                        2. Send “FFFFh” - dummy 16 clocks (the dummy clocks will make FRAM complete any possible ongoing operation and release the bus)

                        3. Send “Start” then “Stop” (it will abort current operation and bring FRAM to idle state)

                         

                        I hope this could address your inquiry.

                        • 9. Re: FRAM : FM24C16B-G : Software reset
                          MaMi_1205306

                          Hi,

                           

                          We have a question in your answer.

                           

                          1.

                          Please tell me the meaning of sending "start" first.
                          If the start can be issued successfully, is the FRAM then inserted to move on to address reception?

                           

                          2.
                          Please tell us why you send 16 clocks of 0xFFFF data.
                          Does that mean that all the data in the FRAM buffer is output?
                          Why 16 clocks and why 0xFFFF data?

                           

                          3.
                          What is the meaning of sending  “Start” then “Stop”?

                           

                          Regards,

                          • 10. Re: FRAM : FM24C16B-G : Software reset
                            ShupingZ_76

                            Hi,

                            Thank you for confirming the sequence.

                             

                            For Q1 (STEP 1), If the START can be issued successfully, the FRAM then inserted to move on to address reception.

                            If FRAM was in write operation, the write operation would be aborted.

                            If FRAM was in read operation, the START would be failed to issue.

                             

                            For Q2 (STEP 2), please allow me to revise the 16 clocks of 0xFFFF to 9 clocks of 0x1FF based on the following reason.

                            If the START was failed to issue, it means that FRAM is in the middle of 8-bit data reading, the CPU needs to issue a min of 8 dummy clocks so that FRAM completes its ongoing byte read and releases the bus. Data 0xFF means that CPU is trying to send No-acknowledge to FRAM when the bus is released.

                            If the START can be issued successfully, the FRAM then inserted to move on to address reception. Data 0xFF will become the slave address. Since 0xFF is an invalid slave address for FM24C16B-G, FM24C16B-G should return No-acknowledge in the 9th clock and the operation is aborted.

                             

                            For Q3 (STEP 3), please see the following picture.

                            I hope this could address your inquiry.