3) What is the meaning of INTR_RX_MASKED? Is it documented somewhere? How is it used in this context?
/* Check for "RX fifo not empty interrupt" */
if((UART_HW->INTR_RX_MASKED & SCB_INTR_RX_MASKED_NOT_EMPTY_Msk ) != 0)
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I think that you need to get TRM (Technical Reference Manual) for these information.
Documentation(s) for PSoC 6 can be found at
In the Documentation Tab > Technical Reference Manual
there are TRM for each family.
So choose TRM and Registers TRM for your device.
For example, If I select TRM for PSoC 61, I can down load them as
PSoC 6 MCU: PSoC 61 Architecture Technical Reference Manual
PSoC 6 MCU: PSoC 61 Register Technical Reference Manual
Now in the Registers Technical Reference Manual
NOT_EMPTY is bit and SW access is "RW1C", which means "write 1 to clear"
This feature is handy, to clear a bit, only writing data with that bit set can clear the bit of the register,
otherwise we have to read the register, clear the bit and write it back to the register.
I think you are right, as far as there is remaining data in the buffer,
not_empty interrupt will be triggered again.
Technical Reference Manual
22.6 SCB Interrupts
Register Technical Reference Manual
Thanks, moto. That is very helpful! I'm still not sure exactly what is meant by "Receiver interrupt masked request," but I'm guessing it might be an interrupt that passed the mask set in the main:
/* Unmasking only the RX fifo not empty interrupt bit */
UART_HW->INTR_RX_MASK = SCB_INTR_RX_MASK_NOT_EMPTY_Msk;
I was able accomplish the "deferred get" by putting
UART_1_HW->INTR_RX_MASK &= ~SCB_INTR_RX_MASK_NOT_EMPTY_Msk;
in ISR_UART and putting
UART_1_HW->INTR_RX_MASK |= SCB_INTR_RX_MASK_NOT_EMPTY_Msk;
after my Cy_SCB_UART_Get. I got lucky that INTR_RX_MASK is RW, not RW1C.
I don't know if this is right, or correct, but it does seem to work.