CE219656 - PSoC 6 MCU UART using Low Level APIs; clearing interrupt

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CaKu_4284131
Level 5
Level 5
50 replies posted 25 replies posted 10 likes received

I am looking at, and running, the UART_Low_Level_User_ISR code sample. I have a question about this function:

/***************************************************************************//**

* Function Name: ISR_UART

********************************************************************************

*

* Summary:

*  This function is registered to be called when UART interrupt occurs.

*  (Note that only RX fifo not empty interrupt is unmasked)

*  Whenever there is a data in UART RX fifo, Get that data and Put it into

*  UART TX fifo which will be transmitted to terminal

...

void ISR_UART(void)

{

    /* Check for "RX fifo not empty interrupt" */

    if((UART_HW->INTR_RX_MASKED & SCB_INTR_RX_MASKED_NOT_EMPTY_Msk ) != 0)

{

        /* Clear UART "RX fifo not empty interrupt" */

UART_HW->INTR_RX = UART_HW->INTR_RX & SCB_INTR_RX_NOT_EMPTY_Msk;       

           

        /* Get the character from terminal */

read_data = Cy_SCB_UART_Get(UART_HW);

...

Questions:

1) How does bitwise AND of SCB_INTR_RX_NOT_EMPTY_Msk (0x4UL) with UART_HW->INTR_RX clear the interrupt? Also, is this the preferred way to clear the interrupt in the ISR?

2) Is it even possible to clear this interrupt if the RX fifo is not empty, or it will it be redriven forever until something like Cy_SCB_UART_Get(UART_HW)empties the fifo? I'd like to defer the get.

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1 Solution
MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Hi,

I think that you need to get TRM (Technical Reference Manual) for these information.

Documentation(s) for PSoC 6 can be found at

https://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6

In the Documentation Tab > Technical Reference Manual

there are TRM for each family.

So choose TRM and Registers TRM for your device.

For example, If I select TRM for PSoC 61, I can down load them as

==================

PSoC 6 MCU: PSoC 61 Architecture Technical Reference Manual

https://www.cypress.com/file/420571/download

PSoC 6 MCU: PSoC 61 Register Technical Reference Manual

https://www.cypress.com/file/455046/download

==================

1)

Now in the Registers Technical Reference Manual

21.1.38 SCB0_INTR_RX

NOT_EMPTY is bit[2] and SW access is "RW1C", which means "write 1 to clear"

This feature is handy, to clear a bit, only writing data with that bit set can clear the bit of the register,

otherwise we have to read the register, clear the bit and write it back to the register.

2)

I think you are right, as far as there is remaining data in the buffer,

not_empty interrupt will be triggered again.

3)

Technical Reference Manual

22.6 SCB Interrupts

Register Technical Reference Manual

21.1.41 SCB0_INTR_RX_MASKED

moto

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4 Replies
CaKu_4284131
Level 5
Level 5
50 replies posted 25 replies posted 10 likes received

Also:

3) What is the meaning of INTR_RX_MASKED? Is it documented somewhere? How is it used in this context?

    /* Check for "RX fifo not empty interrupt" */

    if((UART_HW->INTR_RX_MASKED & SCB_INTR_RX_MASKED_NOT_EMPTY_Msk ) != 0)

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MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Hi,

I think that you need to get TRM (Technical Reference Manual) for these information.

Documentation(s) for PSoC 6 can be found at

https://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6

In the Documentation Tab > Technical Reference Manual

there are TRM for each family.

So choose TRM and Registers TRM for your device.

For example, If I select TRM for PSoC 61, I can down load them as

==================

PSoC 6 MCU: PSoC 61 Architecture Technical Reference Manual

https://www.cypress.com/file/420571/download

PSoC 6 MCU: PSoC 61 Register Technical Reference Manual

https://www.cypress.com/file/455046/download

==================

1)

Now in the Registers Technical Reference Manual

21.1.38 SCB0_INTR_RX

NOT_EMPTY is bit[2] and SW access is "RW1C", which means "write 1 to clear"

This feature is handy, to clear a bit, only writing data with that bit set can clear the bit of the register,

otherwise we have to read the register, clear the bit and write it back to the register.

2)

I think you are right, as far as there is remaining data in the buffer,

not_empty interrupt will be triggered again.

3)

Technical Reference Manual

22.6 SCB Interrupts

Register Technical Reference Manual

21.1.41 SCB0_INTR_RX_MASKED

moto

Thanks, moto. That is very helpful! I'm still not sure exactly what is meant by "Receiver interrupt masked request," but I'm guessing it might be an interrupt that passed the mask set in the main:

    /* Unmasking only the RX fifo not empty interrupt bit */

    UART_HW->INTR_RX_MASK = SCB_INTR_RX_MASK_NOT_EMPTY_Msk;

I was able accomplish the "deferred get" by putting

   UART_1_HW->INTR_RX_MASK &= ~SCB_INTR_RX_MASK_NOT_EMPTY_Msk;

in ISR_UART and putting

   UART_1_HW->INTR_RX_MASK |= SCB_INTR_RX_MASK_NOT_EMPTY_Msk;       

after my Cy_SCB_UART_Get. I got lucky that  INTR_RX_MASK is RW, not RW1C.

I don't know if this is right, or correct, but it does seem to work.

MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Hi,

I'm glad to know that the information was usable.

FYI, I found following description in the TRM 22.6 SCB Interrupts.

001-description.JPG

002-Figure22-44.JPG

moto

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