4 Replies Latest reply on Feb 10, 2020 11:37 AM by JaOs_4375651

    I2C generated code read/write fails due to busy bus but only one master




      The MCU is a CY8C4248AZI-L485, using an I2C component. This is a single master system with two slaves. Occasionally the two slave devices do not communicate and I tracked this down to the generated code in I2C_I2C_MASTER.c. It reads the I2C status register busy bit and returns an error if the bit is a '1'. It's seeing the I2C bus is busy (SCL is low)  but when I read this register the bit is a '0', putting a scope on the SCL line it is not low, it's pulled up as expected. The pull up resistors are pulled up to 1.8V and VDD is 3.3V. I realize 1.8V does not meet the VIH level which caused me to suspect this as the culprit. The pins have a CMOS 1.8V option which is being used but not sure it's supported for this device and/or not supported on port 4. Note that, after power cycle, the I2C bus either fails 100% of time or works 100% of the time, seems it would fail randomly. Any help would be appreciated.