With CMOS the VIH and VOH levels are 0.7*VDD and 0.3*VDD respectively. Please refer page number 18 table 4 of the datasheet.
So, please check by pulling the SCL and SDA lines to VDDD instead of 1.8 volts. If you are still facing the issue, please mention more about the 2 slaves that you are using along with the schematic.
Do you have any issue with pulling the SCL and SDA lines to 3.3 Volts?
The two devices are sensors, sorry I'm not allowed to show schematics. One device has a maximum VDD of 1.98V, nominal 1.8V and will clamp the I2C lines to it's VDD. I just changed the voltage to 2.33 (.7*VDD) and still see the issue. Will try 2.43V...
All the devices in the bus must have the voltage levels for logic 1 and 0 as mentioned by GaneshD_41.
PSoC 4200L provides two SIO pins - P12 and P12 that has programmable switching thresholds and programmable output pull-up voltage capability. They allow interfacing to buses and devices operating at different voltage levels.
We recommend you to use these SIO pins to interface 1.8 V for the I2C bus. Please refer to the pins component datasheet and PSoC 4200 L architecture TRM on how to use SIO pins for your application.
Okay, I suspected the issue was with the levels. The engineer who did this probably assumed it would work since PSoC doesn't show an error if the CMOS 1.8V option is used for those pins (P4.0 and P4.1). There's something in the errata about this but apparently they didn't read. My plan is to use a level shifter but may experiment with P12.0 and P12.1.