4 Replies Latest reply on Feb 10, 2020 2:01 AM by EnPa_1371286

    Kickback from ADC SAR Seq on PSoC 5LP

    EnPa_1371286

      Dear all

       

      I'm experiencing heavy kickback on the reading of the ADC SAR Seq in a CY8C5268AXI-LP047.

       

      I have 6 signals going to the input multiplexer of the ADC.

      Those signals are DC signals from a low impedance source.

      Before entering the PSoC there's a RC low-pass. I'm choosing the components by trial and error to reduce kickback.

       

      The ADC is configured as single-ended with Internal Vref attached to the negative input.

       

      I haven't found any information on the input capacitance of the ADC (that would help with the filter).

      Are those figure known and accesiblle somewhere?

       

      Furthermore, is it possible to control the mux "by hand" or to choose a longer aquisition time, so that the source can settle again before conversion starts?

       

      Cheers,

      Enpa

        • 1. Re: Kickback from ADC SAR Seq on PSoC 5LP
          VasanthR_91

          Hi Enpa,

           

          //I haven't found any information on the input capacitance of the ADC (that would help with the filter).

          Are those figure known and accessible somewhere?//

           

          The ADC sample and hold cap can be around 6.4pF. The capacitance of GPIO can come into picture if you do it that way. Device datasheet has values of these.

           

          //Furthermore, is it possible to control the mux "by hand" or to choose a longer aquisition time, so that the source can settle again before conversion starts?//

          To control the acquisition time you can use SAR0_CSR2/ SAR1_CSR2 register. sample with control bits are present. You can control them to increase your acquisition time to meet your settling time. Kindly check the registers TRM for more details.

           

          Best Regards,
          Vasanth

          • 2. Re: Kickback from ADC SAR Seq on PSoC 5LP
            BoTa_264741

            enpa,

            I believe that you are talking about cross-talk between ADC channels. Standard solution for that in multiplexed operation is to interleave channels with grounded inputs. That is to make 12 input channels and ground each other channel. Now when scanning ADC channels, the grounded pins will discharge any charges left from previous channel.

             

            Secondly, try to remove any capacitors at the ADC Mux inputs. If noise from source is unacceptable, use RC circuit with small C value, e.g. 10-100n, and adjust R to get necessary bandwidth, e.g. R=10k, C=100n, Fc=1/(2PIxRxC)=159Hz. Keep in mind that SAR_ADC input impedance is low (~20k), so increasing R >10k is not recommended.

            /odissey1

            • 3. Re: Kickback from ADC SAR Seq on PSoC 5LP
              WaMa_286156

              In my experiences, the first reading from the SAR can be incorrect, especially if you use cap bypass for sample/hold (which is recommended for stable readings). 

               

              So, if you control the readings with interrupts and software, you can do a second reading to get the right answer.

               

              You can place a SAR, configured for software control, in the schematic and an analog mux, with control lines to a register.  Then hook the EOC (end of conversion) to an interrupt and handle readings and switches in the interrupt.

               

              I have hooked one mux input to ground, and used that to generate an offset that can be used to subtract out any cumulative offsets for temperature variations.

               

              In addition, if you have a 10uf cap bypass on the sample/hold input for the SAR and possibly for the VREF bypass, you will want to do 3 or more readings, depending upon the impedance of the drive circuitry and the speed of conversion.

              • 4. Re: Kickback from ADC SAR Seq on PSoC 5LP
                EnPa_1371286

                Thank you all for the useful hints.

                I ended using a single-input SAR and a firmware controlled mux.

                That solved the problem.

                 

                @BoTa_264741: yes that's the problem I was experiencing. The level between inputs was different and I got the charge stored in the input capacitor of the converter interfering with the next channel upon switching. The source is indeed low impedance, but I have a quite long PCB trace between the source and the microcontroller.

                 

                Again, problem solved, thank you :-)

                 

                Cheers, Enpa