Have you referred to section 1.7.5 of CX3_TRM? If yes, can you let me know what is the value of PLL_CLK in your case?
Yes, I calculated PLL_CLK with the following equation:
PLL_CLK = REFCLK * [(pllFbd + 1)/(pllPrd + 1) ] /(2^pllFRS)
Using the following values:
pllFbd = 62
pllPrd = 1
pllFRS = CY_U3P_CSI_PLL_FRS_500_1000M = 0
So, with this values I obtain PLL_CLK = 604.8Mhz. for this reason i don't know why i have a lower frequency on the mClkCtl pin, becasue into the typedef struct CyU3PMipicsiCfg_t declaration it shows that mClkOutput = PLL_Clock / mClkRefDiv.
The field 'mClkCtl' of the mipi config structure is incorrect. In your case it is set to 0xFFFF
MCLK out frequency = (PLL_CLK) / (MCLK_divider) / (HighByte(mClkCtl) + LowByte(mClkCtl)). In your case it would become
~ 604MHz / (2 * (256+256))
So, please correct the field accordingly.