8 Replies Latest reply on Jul 9, 2020 2:57 PM by AlbertB_56

    HyperRAm IP-Core FPGA timing closure issue. Help requested

    AlMa_4596461

      Hi,

      I am trying to compile the HyperBus Memory Controller IP - Release version V2L4_02  in a Xilinx Artix 7 FPGA device. I get a lot of timing errors. When digging in the design, I see a lot of the failing path that seems to be intended asynchronous as they are re-synchronized. My first guess is most of these timing path should be ignored during the timing analysis and set as false path.  I find it risky to set false path on these failing path as I am not familiar with the design and  I do not want to over-constraint and make Vivado ignore valid timing paths.

       

      The sdc file provided with the IP-Core declares clock domains asynchronous between each others. But deeper in the design, clk and ip_clk domain are connected together in the file rpc2_ctrl_mem.v. By doing so, the 2 clock domains become a unique domain and therefore path between the 2 get analyzed.  I suspect that some unnecessary re synchronization logic should be removed on these path or false path constraints should be added.

       

       

      As someone encountered such issue? Is it possible to find a list of what should be declared as false path?

       

      Best Regards,

       

      Alain