2 Replies Latest reply on Jan 29, 2020 3:10 AM by PY_21

    Link layer TX size maxes out at 92


      I am trying to transmit 251 byte packets from my PSoC 6 Kit (CY8CKIT-062-BLE). Whenever I have the "link layer max TX size (bytes)" set to any value 93 or larger, Cy_BLE_Start returns CY_BLE_MEMORY_ALLOCATION_FAILED.


      I've found instructions regarding how to change the total stack and heap by setting the __STACK_SIZE and __HEAP_SIZE compiler macros, but those don't change whether the BLE stack starts up. I'm using the PSoC 6 Kit (CY8CKIT-062-BLE).

        • 1. Re: Link layer TX size maxes out at 92

          I've fixed the memory issue by setting the RX packet size to the same as my TX packet size. That works for me as long as the max RX is just an allocation and the true RX used in the connection is smaller. My device doesn't receive much data, but needs to send notifies.


          What's interesting about this to me is that I this causes CY_BLE_STACK_RAM_SIZE to grow, but that doesn't affect the memory allocation failure. I can shrink it by disabling features in BLE widget in the schematic, and a 93-byte TX / 27-byte RX will still fail even though the claimed RAM size is less than the size it was using in the case that works 92-byte TX / 27-byte RX.


          I have a stack trace. The failure occurs somewhere inside <mint_buf_mgmt_create_pool>, which I've added on top of the call stack by hand:

          1. 0 <mint_buf_mgmt_create_pool>
          2. 1 le_initialize_buffers() ?????? ?????? 0x10018924 (All)
          3. 2 CyBle_ControllerInit() ?????? ?????? 0x10008016 (All)
          4. 3 Cy_BLE_StackInit() ?????? ?????? 0x100066BA (All)
          5. 4 Cy_BLE_Enable() Generated_Source\PSoC6\pdl\middleware\ble\cy_ble.c 364 0x10002CBE (All)
          6. 5 Cy_BLE_Start(cy_ble_callback_t callbackFunc = 0x0, cy_ble_callback_t callbackFunc@entry = 0x0) Generated_Source\PSoC6\BLE.c 152 0x1000094E (All)
          7. 6 main() main_cm0p.c 43 0x10000284 (All)


          The exact addresses aren't quite right, but I'm sure that <le_initialize_buffers> is what's failing. The stackInitParam looks like:


          1. stackInitParam  {...}   0x08023FC0 (All)    struct { cy_ble_app_ev_cb_t CyBleAppCbFunc; cy_stc_ble_stack_mgr_mem_cfg_param_t memParam; cy_stc_ble_stack_config_param_t stackConfig; }
          2. CyBleAppCbFunc  0x00000000  0x08023FC0 (All)    void (*)(cy_en_ble_event_t, void *)
          3. memParam    {...}   0x08023FC4 (All)    struct { uint8_t *memoryHeapPtr; cy_stc_ble_stk_app_data_buff_t *dataBuff; uint16_t totalHeapSz; uint8_t totalDataBufferPools; const uint8_t *bleStackFlashPointer; uint32_t bleStackFlashSize; }
          4. memoryHeapPtr   0x080005D4 (All)    0x08023FC4 (All)    uint8_t *
          5. *memoryHeapPtr  0x20 ' '    0x080005D4 (All)    unsigned char
          6. dataBuff    0x00000000 (All)    0x08023FC8 (All)    cy_stc_ble_stk_app_data_buff_t *
          7. bufferSize      0x00000000 (All)    unsigned short
          8. bufferUnits     0x00000002 (All)    unsigned short
          9. totalHeapSz 0x0E3C  0x08023FCC (All)    unsigned short
          10. totalDataBufferPools    0x00 '\000' 0x08023FCE (All)    unsigned char
          11. bleStackFlashPointer    0x00000000 (All)    0x08023FD0 (All)    const uint8_t *
          12. *bleStackFlashPointer       0x00000000 (All)    unsigned char
          13. bleStackFlashSize   0x00000000  0x08023FD4 (All)    unsigned long
          14. stackConfig {...}   0x08023FD8 (All)    struct { cy_stc_ble_dle_config_param_t dleConfig; cy_stc_ble_l2cap_config_param_t l2capConfig; cy_stc_ble_privacy_1_2_config_param_t privacyConfig; cy_stc_ble_bonded_device_list_config_param_t bondListConfig; cy_stc_ble_white_list_config_param_t whiteListConfig; uint16_t featureMask; uint16_t featureHeapReq; uint8_t maxBleConnections; }
          15. dleConfig   {...}   0x08023FD8 (All)    struct { uint16_t dleMaxTxCapability; uint16_t dleMaxRxCapability; uint8_t dleNumTxBuffer; uint8_t dleNumRxBuffer; }
          16. dleMaxTxCapability  0x005D  0x08023FD8 (All)    unsigned short
          17. dleMaxRxCapability  0x001B  0x08023FDA (All)    unsigned short
          18. dleNumTxBuffer  0x03 '\003' 0x08023FDC (All)    unsigned char
          19. dleNumRxBuffer  0x04 '\004' 0x08023FDD (All)    unsigned char
          20. l2capConfig {...}   0x08023FDE (All)    struct { uint8_t l2capBufferPerConn; }
          21. l2capBufferPerConn  0x00 '\000' 0x08023FDE (All)    unsigned char
          22. privacyConfig   {...}   0x08023FDF (All)    struct { uint8_t resolvingListSize; }
          23. resolvingListSize   0x10 '\020' 0x08023FDF (All)    unsigned char
          24. bondListConfig  {...}   0x08023FE0 (All)    struct { uint8_t bondListSize; }
          25. bondListSize    0x00 '\000' 0x08023FE0 (All)    unsigned char
          26. whiteListConfig {...}   0x08023FE1 (All)    struct { uint8_t whiteListSize; }
          27. whiteListSize   0x10 '\020' 0x08023FE1 (All)    unsigned char
          28. featureMask 0x006B  0x08023FE2 (All)    unsigned short
          29. featureHeapReq  0x0E3C  0x08023FE4 (All)    unsigned short
          30. maxBleConnections   0x01 '\001' 0x08023FE6 (All)    unsigned char
          • 2. Re: Link layer TX size maxes out at 92

            Hello NiLe_4630071 ,


            Please update the PDL to latest version in the PSoC Creator. Please refer the below link for downloading the Latest version of PDL.

            Link: https://www.cypress.com/design-guides/peripheral-driver-library-pdl-psoc-creator

            In PSoC Creator, Right click on the Project -> Goto 'Build settings' -> 'Peripheral Driver Library' and add the path of newer version in custom tab as shown in attached image.



            P Yugandhar.

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