UART

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saku_4625426
Level 3
Level 3

Hello,

I am trying to print the UART Debugprints of FX3 using Teraterm.But the problem is that I am getting garbage data in teraterm as attached.I checked UART Configurations such as BaudRate,Parity etc on both sides i.e PC and FX3.But Still I am getting the same.Can anyone help me for this?

Regards,

Sai Kumar.

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1 Solution

Hello Sai kumar,

Please refer to this thread debug prints incorrect instead getting random data with similar problem. The issue got resolved by changing the cable.

- Please check whether the cable UART- USB is proper

- If you board is having pins 43-46 as UART, the lpp mode should be default .

Regards,

Rashi

Regards,
Rashi

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12 Replies
Rashi_Vatsa
Moderator
Moderator
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5 likes given 500 solutions authored 1000 replies posted

Hello Sai kumar,

Please refer to this KBA Use of CyU3PDebugPreamble() API – KBA227492  and disable the debug preamble

Regards,

Rashi

Regards,
Rashi
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Hello,

Please see the below API in which Preamble is disabled.

void

CyFxSlFifoApplnDebugInit (void)

{

    CyU3PUartConfig_t uartConfig;

    CyU3PReturnStatus_t apiRetStatus = CY_U3P_SUCCESS;

    /* Initialize the UART for printing debug messages */

    apiRetStatus = CyU3PUartInit();

    if (apiRetStatus != CY_U3P_SUCCESS)

    {

        /* Error handling */

        CyFxAppErrorHandler(apiRetStatus);

    }

    /* Set UART configuration */

    CyU3PMemSet ((uint8_t *)&uartConfig, 0, sizeof (uartConfig));

    uartConfig.baudRate = CY_U3P_UART_BAUDRATE_9600;

    uartConfig.stopBit = CY_U3P_UART_ONE_STOP_BIT;

    uartConfig.parity = CY_U3P_UART_NO_PARITY;

    uartConfig.txEnable = CyTrue;

    uartConfig.rxEnable = CyTrue;

    uartConfig.flowCtrl = CyFalse;

    uartConfig.isDma = CyTrue;

    apiRetStatus = CyU3PUartSetConfig (&uartConfig, 0);

    if (apiRetStatus != CY_U3P_SUCCESS)

    {

        CyFxAppErrorHandler(apiRetStatus);

    }

    /* Set the UART transfer to a really large value. */

    apiRetStatus = CyU3PUartTxSetBlockXfer (0xFFFFFFFF);

    if (apiRetStatus != CY_U3P_SUCCESS)

    {

        CyFxAppErrorHandler(apiRetStatus);

    }

    /* Initialize the debug module. */

    apiRetStatus = CyU3PDebugInit (CY_U3P_LPP_SOCKET_UART_CONS, 8);

    if (apiRetStatus != CY_U3P_SUCCESS)

    {

    CyU3PDebugPreamble(CyFalse);

    CyFxAppErrorHandler(apiRetStatus);

    }

}

Regards,

Sai Kumar.

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Hello Sai kumar,

The API is called inside the condition when debug init fails. If debug init doesn't fail, the API will not be called

The API should be called after CyU3PDebugInit API

   /* Initialize the debug module. */

    apiRetStatus = CyU3PDebugInit (CY_U3P_LPP_SOCKET_UART_CONS, 8);

    if (apiRetStatus != CY_U3P_SUCCESS)

    {

        CyFxAppErrorHandler(apiRetStatus);

    }

    /* Disable the header associated with debug logs. */

   CyU3PDebugPreamble (CyFalse);

Regards,

Rashi

Regards,
Rashi
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Hello,

Now i did as you mentioned in the above reply.Now I am not getting anything in Teraterm.

I am attaching my firmware below.Can you please figure it out what is the problem?

Regards,

Sai Kumar.

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Hello,

After changing  io configuration ,now  i'm getting garbage values in tera term.

#if (CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT == 0)

    io_cfg.isDQ32Bit = CyFalse;

    io_cfg.lppMode   = CY_U3P_IO_MATRIX_LPP_DEFAULT;       //CY_U3P_IO_MATRIX_LPP_UART_ONLY

#else

    io_cfg.isDQ32Bit = CyTrue;

    io_cfg.lppMode   = CY_U3P_IO_MATRIX_LPP_DEFAULT;

#endif

What to do to get debug prints in tera term?

Regards,

Sai Kumar

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Hello Sai Kumar,

Please let me know which pins are you using for UART.

datasheet.PNG

- For 32 bit  bus  configuration  and lpp mode as default

PINS[53] -[56] are UART pins

- For 16 bits bus configuration and lpp mode as default

PINS[46] -[49] are UART pins

In the firmware you shared in previous response the bus configuration is 16 bit and lpp mode as UART ONLY In this configuration

PINS[53] - [56] are UART pins

Regards,

Rashi

Regards,
Rashi
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Hello,

In FPGA side i'm using pins 46 -49 as UART Pins  and  fx3 side lpp mode is lpp mode as default.

Snapshots of io config and FPGA side MIO config as shown below,

Regards,

Sai Kumar

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Hello Sai Kumar,

For FX3 part (CYUSB301x), 16 bit configuration and lpp mode as default.

Pins [46]-[49] are used as UART on FX3 side.

I didn't understand you saying pins on FPGA side.

Please refer to this thread fx3 uart

Regards,

Rashi

Regards,
Rashi
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Hello Sai Kumar,

Please let me know which FX3 part number you are using.

Regards,

Rashi

Regards,
Rashi
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Hello,

Please let me know which FX3 part number you are using.

     CyUSB3035

Regards,

Sai Kumar

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Hello Sai Kumar,

Please refer to this KBA and try implementing it FX3 UART Prints Garbage Data During JTAG Debugging - KBA86728 if you are using JTAG.

Can you try getting debug prints without using JTAG.

Also share the schematics of UART connection (UART PINS >> UART connector)

Regards,

Rashi

Regards,
Rashi
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Hello Sai kumar,

Please refer to this thread debug prints incorrect instead getting random data with similar problem. The issue got resolved by changing the cable.

- Please check whether the cable UART- USB is proper

- If you board is having pins 43-46 as UART, the lpp mode should be default .

Regards,

Rashi

Regards,
Rashi
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