FX3 assignment of address A1, A0 for 8bit GPIF

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NoAr_1540581
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Distributor - Macnica (Japan)
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Hello

If the assignment of address A1, A0 is 32bit or 16bit so far, it will be configured as follows.

GPIO [28] / CTL [11] / A1
GPIO [29] / CTL [12] / A0

Q)

This time, the GPIF of FX3 will be configured with an 8-bit bus.
In that case, the pins are assigned as shown below.
Do I need to do anything manually to assign it to the same location as 16bit / 32bit?

GPIO [10] / DQ [8]
GPIO [11] / DQ [9]

Best Regards

Arai

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HirotakaT_91
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The beginner who would like to operate GPIF-II interface, I recommend to read Slave FIFO interface document.

It's appplication note is called "Designing with the EZ-USB® FX3™ Slave FIFO Interface" that number is AN65974.

https://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-inte...

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Regards,

Hirotaka Takayama

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HirotakaT_91
Moderator
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500 replies posted 250 replies posted 100 replies posted

The beginner who would like to operate GPIF-II interface, I recommend to read Slave FIFO interface document.

It's appplication note is called "Designing with the EZ-USB® FX3™ Slave FIFO Interface" that number is AN65974.

https://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-inte...

pastedImage_0.png

Regards,

Hirotaka Takayama

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NoAr_1540581
Level 5
Level 5
Distributor - Macnica (Japan)
5 solutions authored 250 sign-ins 100 replies posted

Thank you for your reply.

As a result, they are using it as 32-bit bus mode(GPIO[28]:A1, GPIO[29]:A0) of SlaveFiFO. However, since the actually required data is only the lower 8 bits, the extra 24-bit GPIF terminal is not connected.
--- Because they are using their current board ---

Q1) Since the upper unused bits (DQ [8] to DQ [31]) are not used( not connected), the value can be undefined, but is it necessary to fix the logic outside the chip? Also, is there an internal Pull-UP?

Q2) As described above, if DQ [8] to DQ [31] are not connected, are there any possible problems such as the HOST not COMMIT, etc?

Best Regards

Arai

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If they use only lower 8bit, they can set it on GPIF-II designer. I am not clear why they set 32 bit.

FX3  has  internal  firmware-controlled  pull-up  or  pull-down resistors on all digital I/O pins. An internal 50-kohms resistor pulls the pins high, while an internal 10-kohms resistor pulls the pins low to  prevent  them  from  floating.

The default state of the IOs at power-on and after reset is tristate. You can set registers or use FX3 SDK API CyU3PGpioSetIoMode to set pull-up or pull-down on an I/O pin.

Please refer to the FX3 datasheet and TRM 4.1.3 GPIO Pull-up and Pull-down. https://www.cypress.com/documentation/technical-reference-manuals/ez-usb-fx3-technical-reference-man...

Best regards,

Hirotaka Takayama

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NoAr_1540581
Level 5
Level 5
Distributor - Macnica (Japan)
5 solutions authored 250 sign-ins 100 replies posted

>If they use only lower 8bit, they can set it on GPIF-II designer. I am not clear why they set 32 bit.

お客様の現状の評価用基板の接続構成が32bit構成でGPIF部分(A0A1)が接続されておりますので、GPIFのPIN接続は変更しないでそのままの構成(32bit)で使用したいとの事です。但し、不要な24bitのGPIF部分は未接続となっております。

データの取り出し(下位8bit)、加工は ホスト側で行うと、24bit未接続のまま、32bitモードでホストとと通信した場合、正常にコミットしてDMA転送自体は正常に行われますでしょうか?

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No. Read AN75779 3.5  GPIF II State Machine and modify the counter.

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