3 Replies Latest reply on Jan 14, 2020 12:47 AM by PradiptaB_11

    CY7C4141 (QDR-IV) without QKB0 & QKB1 clock output

    chsi_4622291

      CY7C4141 have enabled port A and port B by asserting A[12:11]=11 at reset rising edge (assured by Oscilloscope). But we test the SRAM without QKB0 , QKB1 output all the time , and QKA0,QKA1 are normal.

      Is that state normalized? It seems the QDR-IV be put into Fixed Port Mode or Only Port A Enable mode, why?

      Now the CY7C4141 fails on Write deskew.

        • 1. Re: CY7C4141 (QDR-IV) without QKB0 & QKB1 clock output
          PradiptaB_11

          Hi,

           

          The port A and port B of the QDR IV are enabled by default and they need not be enabled by asserting any Address lines. Also the datasheet does not specify any such techniques so there is no need to do so( did you find this in the datasheet ?). They are independent bidirectional data ports.

          Now the address and control inputs for port A get clocked into the device at the rising edge of CK and same happens for port B at falling edge of CK.

          Now if you are writing into the device the data needs to be clocked in using the DKA data input clock for port A and DKB data input clock for port B.

          Now if you are reading from the device the data needs to be clocked out using the QKA or QKB clock signals for port A and port B respectively.

           

          By not using DKB and QKB you are making the device a single port device. If you want to access and use both the ports then you have to provide clocking signals to DKB and QKB.

           

          If you still have issues you can provide us the scope shots of your read and write operations so that we can debug the issue.

           

          Thanks,

          Pradipta.

          • 2. Re: CY7C4141 (QDR-IV) without QKB0 & QKB1 clock output
            chsi_4622291

            thanks for your responding.

            In fact,I meet a problem. When I do calibration to QDR IV by FPGA, it always fails on writing DQ to DK deskew. but read deskew is always fine.

            so i test the signal by Oscilloscope and found QKA0 & QKA1 are always normal but QKB0 & QKB1 are absent. These four clocks are sent by QDR IV.

            So, my question is, after power up, should QKA and QKB be always present by default?

            As the QDR IV fail on calibration, now I can not do read and write operations.

            • 3. Re: CY7C4141 (QDR-IV) without QKB0 & QKB1 clock output
              PradiptaB_11

              Hi Chen,

               

              I suggest you to use our AN on QDR IV. It will give you an idea on the clocking signals description (section 3.1) and the deskew sequence(section 3.3). Kindly follow section 3.3 step by step as described let us know if you face any issues.

              https://www.cypress.com/file/46581/download

               

              Thanks,

              Pradipta.