1 2 3 Previous Next 42 Replies Latest reply on Mar 4, 2020 3:51 AM by RashiV_61

    FX3 to FPGA via GPIF II Interface

    poas_4520791

      Hi,

       

      I have to  transfer data from FX3 to FPGA  using GPIF II interface.I'm using the firmware that is in  AN65974 and i will give data through control center.But i'm able to receive only starting 2 bytes,the remaining bytes are missing,as shown in below snapshot.What may be the reason for this,kindly anyone  let me know the issue. 2.PNG

       

       

      Regards,

      Aswini

        • 1. Re: FX3 to FPGA via GPIF II Interface
          RashiV_61

          Hello Aswini,

           

          Can you probe the PCLK line, for reference, to know the number of bytes read.

          Also let me know, you have programmed the FX3 for which transfers: Stream_IN_OUT or SF_shrt_ZLP?

           

          Can you program the FX3 with the .img file attached  and keep the data size as a multiple of 1024 in USB3 or 512 in USB2. Probe the lines at GPIF interface and share the results.

           

          Regards,

          Rashi

          • 2. Re: FX3 to FPGA via GPIF II Interface
            poas_4520791

            Hello,

             

            I have programmed the fx3 with the .img file which you gave with that FX3 isn't detecting in the control center.

            can you check the firmware attached below.

             

             

             

             

            Regards,

            Aswini

            • 3. Re: FX3 to FPGA via GPIF II Interface
              RashiV_61

              Hello Aswini,

               

              Please let us know are you programming the FPGA  with .bit file which is given with AN65974 application note.

              If yes, the .bit file will not support transfers (reading) like 12 bytes, 2 bytes that you are trying. The .bit file supports full packet transfers as mentioned  table 6 under section 11.5.1.

               

              You have to develop customize FPGA .bit file for reading transfers like this.

               

              Regards,

              Rashi

              • 4. Re: FX3 to FPGA via GPIF II Interface
                poas_4520791

                Hello,

                 

                Please let us know are you programming the FPGA  with .bit file which is given with AN65974 application note.

                I'm  using  different bit file (zynq FPGA).

                 

                Regards,

                Aswini

                • 5. Re: FX3 to FPGA via GPIF II Interface
                  RashiV_61

                  Hello Aswini,

                   

                  The FPGA programming (.bit file in the folder with AN 65974) is done such that the FPGA can only read full packets (1024 bytes - USB 3.0 and 512 bytes - USB 2.0).

                  You need to develop your own FPGA code (.bit file) to short packets.

                   

                  Also ,the FPGA state machine switched to read mode only when the status of the switches are as mentioned below. If your FPGA (ZYNC) board will not have switches at same positions, hence the read mode cannot be selected in such case.

                  fpga_1.PNG

                  So you need to develop your customized FPGA bit file

                   

                  Regards,

                  Rashi

                  • 6. Re: FX3 to FPGA via GPIF II Interface
                    poas_4520791

                    Hi,

                     

                    I have developed custom bit file and set the FPGA transfer mode as Stream Bulk OUT ,so we are getting  first 2bytes from fx3 to fpga.

                    I cannot probe pclk from fpga as it was showing some error in fpga side.

                    What may be the reason for not getting the remaining bytes.please let me know.

                     

                    Regards,

                    Aswini

                    • 7. Re: FX3 to FPGA via GPIF II Interface
                      RashiV_61

                      Hello Aswini,

                       

                      We need to know the for how many clock cycles does the SLRD is pulled low. Without clock cycles it is difficult to say the reason for the problem. There is a possibility that 2 bytes of data is read because the SLRD is not pulled low for enough time.

                      Because the time period SLRD will be pulled low, the data can be read by the FPGA from the GPIF line. It would be good to get the PCLK traces.

                      As per the traces shared in the response 17 of the thread Data from FX3 to FPGA is repeating continuously SLRD is not going low.

                      If you say 2 bytes are read, SLRD should be asserted Low for that

                      Condition to be met for data read

                      SLWR : High

                      SLRD : Low;

                      SLCS: Low

                      SLOE : Low

                      PKTEND: High

                       

                      Please share the traces with PCLK and the above GPIF interface lines meeting  above mentioned conditions .

                       

                      Regards,

                      Rashi

                      • 8. Re: FX3 to FPGA via GPIF II Interface
                        poas_4520791

                        Hello,

                         

                        I'm getting the traces as below,

                         

                         

                         

                        Regards,

                        Aswini

                        • 9. Re: FX3 to FPGA via GPIF II Interface
                          RashiV_61

                          Hello Aswini,

                           

                          Thanks you for the traces.

                          Please let me know the time for which SLRD is asserted low.

                          Also confirm that these traces are taken when FX3 is programmed with the firmware shared in response 16 of this thread Data from FX3 to FPGA is repeating continuously

                           

                          As per the default state machine (GPIF II),  data is driven to GPIF II lines till the time SLRD is low. As soon as SLRD the goes high the data won't be driven.

                           

                          From the traces you shared flag c is LOW every time (which means buffer is empty). Please confirm there are no modifiactions done with flag c polarity.  Flag C should be high at first as soon as you read the data from the DMA buffer it should go low (which shows the buffer is empty). On reading the Flga c the FPGA should assert SLRD high (which means stop reading from that socket/buffer).

                           

                           

                           

                           

                          Regards,

                          Rashi

                          • 10. Re: FX3 to FPGA via GPIF II Interface
                            poas_4520791

                            Hello,

                             

                            The SLRD signal  is getting triggered as shown in below snapshot ,but i'm receiving only 2 bytes of data when SLRD is low.I'm using the default firmware with that i just modified GPIF II interface(state machine and polarity of flags as active high),in FPGA(Zynq)  side i'm using customized bit file not the one in AN65974.With the default firmware i'm getting FFFF so i made these changes.

                             

                            rd_trigger.PNG

                             

                            The state machine which i have modified is below,

                            SMachine.PNG

                             

                             

                            kindly  let me know the solution for this issue.

                             

                             

                             

                            Regards,

                            Aswini

                            1 of 1 people found this helpful
                            • 11. Re: FX3 to FPGA via GPIF II Interface
                              poas_4520791

                              Hello,

                               

                              I have one more doubt , through Control center i have sent some bytes and in FPGA side i'm receving 2 bytes .if i sent the another data again through control center i'm able to receive 4 bytes in FPGA side(previous data 2 bytes and present data 2 bytes) as shown below,

                              4 bytes.PNG

                               

                              What may the reason for this?

                               

                              Regards,

                              Aswini

                              • 12. Re: FX3 to FPGA via GPIF II Interface
                                RashiV_61

                                Hello Aswini,

                                 

                                For this you can check the DMA buffer contents.

                                When you get the PROD event (i.e. received the data from USB) you can call the CyU3PDmaMultiChannelGetBuffer  (in the DMA call back)and store contents of Dma buffer and later get that buffer value printed. So that we can know what exactly is in the buffer and what is the FPGA reading.

                                 

                                Regards,

                                Rashi

                                • 13. Re: FX3 to FPGA via GPIF II Interface
                                  poas_4520791

                                  Hello,

                                   

                                  Here is a snippet i used to check no.of buffers get transmitted,i have checked this before using   microsoft visual studio the  txcount got incremented but with that (microsoft visual studio) there is some issue.

                                   

                                    if( type == CY_U3P_DMA_CB_CONS_EVENT)

                                        {

                                        rxcount++;

                                        }

                                      if( type == CY_U3P_DMA_CB_PROD_EVENT)

                                            {

                                            txcount++;

                                            }

                                   

                                   

                                  So,can you tell me another solution to solve this problem.

                                   

                                  Regards,

                                  Aswini

                                  • 14. Re: FX3 to FPGA via GPIF II Interface
                                    RashiV_61

                                    Hello Aswini,

                                     

                                    I am not sure why do you use Microsoft Visual Studio. You can used UART debug prints to print the content (or first two bytes) of DMA buffer and not the how many times the PROD events occur.

                                    Did you get the  rxcount?

                                    Please confirm that UART block is enabled in your firmware. If yes you can use UART for debug purpose. Print the values of these variable or get the DMA buffer contents and print the value.

                                     

                                    If not, get the DMA buffer contents using CyU3PDmaMultiChannelGetBuffer and you can send this buffer (to USB) using a vendor command. When you send the vendor command you will receive the DMA buffer contents.

                                     

                                    Regards,

                                    Rashi

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