Entire FPGA configuration file (.bin file) is not copied to FX3's internal RAM before programming it to SPI Flash. When the vendor command VND_CMD_SLAVESER_CFGLOAD (0xB2) is received, FX3 comes to know the file size that is going to be received. If you see the 0xB2 vendor command handling, CY_FX_CONFIGFPGAAPP_START_EVENT event is set - which will cause the call - CyFxConfigFpga(filelen);
If you check CyFxConfigFpga(), you can see that FX3 keeps receiving each buffer from USB (which is of size 1KB) and writes to the SPI Flash. That is, receiving data from USB and programming the SPI Flash keeps happening simultaneously.
After the programming of SPI Flash is done, 0xB1 vendor command is issued to switch FX3's operation from programming mode to Slave FIFO mode.
I want to be more specific. The PC(Host USB) to download the FPGA_Config.bin file to FX3 via EP (USB-CPU) with file size (2.8MB). There is no
The programming FPGA is done via SPI using SPI_SSn as the PROGRAM_B signal to start FPGA programming and there is NO SERIAL SPI FLASH involved.
The programming command as set by host (0xB2) and received by FX3 firmware to trigger the programming mode.
What I don’t see is the DONE signal from FPGA. Here I have observed the followings :
1. The EP is configured for 1 burst of 1K (or size=1024). However; I noticed if I increase dmaCfg.size from 1024 to 2048 etc. then the programming time
Is decreased accordingly. Is it true ? What about buffer count “dmaCfg.count” , does it have any effect on the programming timing ? The thing I don’t
understand is the mechanics of throttling between fetching data from EP to DMA channel to programming. Is it automatic or how was it handled in hardware
to guarantee overrun/underrun is not happening ?
1. Is Little or Big Endiannes playing the role when downloading the programming data ?
2. What about the STARTUP many clocks cycles required by FPGA before the FPGA is live and DONE is acknowledged ? How does it handle by SPI engine when SPI_CLK
just stops right at the end of file size received ?
1. Followings are the GPIO signals I used for programming interface for Xilinx Spartan6 :
FPGA_PROGRAM_B = GPIO 45
FPGA_CCLK = SPI_SCK (GPIO 53)
FPGA_SDIN = SPI_MOSI (GPIO 56)
FPGA_INIT = GPIO 50
FPGA_DONE = GPIO 27
The difference is I do not use SPI_SSN as per AppNote for FPGA_PROGRAM_B and instead using GPIO 45. However; the code is still have ssnCtrl to be controlled by FW
To make sure it is in sync with clock. But I preceded the SSn signaling with :
CyU3PGpioSimpleSetValue (FPGA_PROGRAM_B, CyFalse);
apiRetStatus = CyU3PSpiSetSsnLine (CyFalse);
All other GPIO signals are configured as : CyU3PGpioSetSimpleConfig() and CyU3PDeviceGpioOverride()
The fact that I see the trails of SPI_CLK until the programming stop and measure approximately the time versus the SPI configuration clock and file size then I know it is
working properly and currently set at 25MHz.
1. I want to understand the relationship between SPI_CLK rate versus settings for DMA size and buffer count.
(I should not have used SPI Flash in my last comment. Sorry for that. But the rest of the comment holds. I just meant programming via SPI)
1. Yes, increasing DMA buffer size will decrease the programming time as waiting time for the data from USB will decrease. The mechanism is - Data from the USB Endpoint reaches DMA buffers through USB socket after which CPU needs to use the SPI hardware registers to transfer the data out of SPI lines. If the DMA buffers allocated to the USB to CPU channel gets filled, then the endpoint would issue NRDY to the Host thereby not accepting new data till atleast one buffer is available.
Effect of increasing the buffer size: Let's say there are two buffers filled with data available to CPU to be sent out to SPI. Then after sending out the first buffer and while sending out second buffer, endpoint fills the free buffer. So, bigger the buffer size, more the time taken to empty it by the CPU.
2. Endianness should be configured during SPI Block initialization and it has nothing to do with the programming duration discussed above.
3. Relation between SPI Clk and DMA: As the SPI clock rate increases, quicker the rate at which DMA buffer is emptied by CPU.