According to the Datasheet of Status Register,
Sticky – Goes high on the rising edge of the Clock (if the status input signal is high). It
goes low after the Status register is read.
If we read the value of Sticky bit, the value goes to low = 0.
Since your project seems to be very complicated to me,
I made a simple test project with following schematic with CY8CKIT-059.
When I ran the program, the Tera Term log was
The values are from left to right
address bit (input)
value of transparent Status Reg
value of Sticky Status Reg
It seems that the transparent value change immediately with the input,
but Sticky bit value change only after the clock raises.
Meantime, after reading the value of the Sticky bit returned to 0.
So I imagine that
(1) every time ReadMemory_Status block is executed, the AddressByte0 value returns to 0
(2) Since both AddressByte0 and ReadMemory are clocked by ph2Clk
the program may read value before AddressByte0 finishes updating the value.
If my assumption is correct, delaying the clock to ReadMemory a few cycles by using DFF or something may fix the problem.
And if my assumption is not correct, I'm sorry for wasting your time.
Thank you Motoo. But I don't see how reading the ReadMemory SR would cause the AddressByte0 SR to clear.
> But I don't see how reading the ReadMemory SR would cause the AddressByte0 SR to clear.
It's reading AddressByte0 which clears the AddressByte0's sticky bit.
So I think that when next line is called, the sticky bit(s) of AddressByte0 SR are cleared.
DataOut_Control = *(uint8_t *) (*(reg32 *) AddressByte0_Status_PTR);
P.S. attached is the datasheet of Status_Reg, please refer to the page 3, Mode > Sticky (Clear on Read)
CyStatusReg_v1_90.pdf 221.1 K