6 Replies Latest reply on Jan 6, 2020 1:26 AM by guta_2945091

    CYW20706 PWM Clk

    guta_2945091

      Dear,

      When I use CYW20706, the PWM part encounters some problems. I need two PWMs, PWM0 & PWM2. They use ACLK1 & ACLK0 as the clock. Is this feasible? Now I can only use one of the clocks ACLK1 or ACLK0.

        • 1. Re: CYW20706 PWM Clk
          WinstonF_61

          Hi,

           

          For CYW20706 ACLK1 is used as an input clk to the PWM block. Refer to the comments for the 'wiced_hal_pwm_start' API in the wiced_hal_pwm.h file (checked this in WICED 6.3).

           

          /// (!) Note that if you use PMU_CLK instead of LHL_CLK, a call to
          ///     wiced_hal_aclk_enable() is required. When configuring aclk,
          ///     ACLK0 is not available for use with PWM--only ACLK1.
          

           

          The sample code under WICED (apps/snip/hal/pwm) uses the same configuration. This also means the same ACLK1 frequency will be applied as an input to all PWM blocks.

           

          Regards

          Winston

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          • 2. Re: CYW20706 PWM Clk
            guta_2945091

            Hi,Winston:

                     thank you for your reply,there is another problem. When testing the PWM, we found that when the duty cycle is very small, the output is not normal. such as

             

            #define PWM_INP_CLK_IN_HZ   (512*1000)

            #define PWM_FREQ_IN_HZ      (100000)

            #define PWM_DUTY_CYCLE      (10)

             

            All we see on the oscilloscope is low. However, when the duty cycle is set to 99, the waveform is normal, so our test equipment is considered to be problem-free.

            • 3. Re: CYW20706 PWM Clk
              XinghaoZ_26

              This is a known problem with the PWM. There are two ways for the workaround.

              1. Limit the PWM duty to 1%~99% as the output has little difference.

              2. When you need 0% or 100% output, change the Pin to GPIO ouput and output high or low directly.

              • 4. Re: CYW20706 PWM Clk
                guta_2945091

                HI,Owen

                          thank you for your reply,However, I tested that the duty cycle is less than 15, and the waveform cannot be output normally.

                • 5. Re: CYW20706 PWM Clk
                  XinghaoZ_26

                  There is some thing wrong with your PWM parameter.

                  #define PWM_INP_CLK_IN_HZ   (512*1000)

                  #define PWM_FREQ_IN_HZ      (100000)

                  #define PWM_DUTY_CYCLE      (10)

                   

                  The input clock is 512*1000, but the PWM_FREQ is 100000. Then the largest PWM Period should be PWM_INP_CLK_IN_HZ/PWM_FREQ_IN_HZ, which is 5. Please try to set the PWM_FREQ_IN_HZ to 1000.

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                  • 6. Re: CYW20706 PWM Clk
                    guta_2945091

                    Ths Owen ,thank you for your reply