3 Replies Latest reply on Jan 15, 2020 11:43 AM by NiMc_4245981

    CCG3 resetting after turning on VBUS_C_CTRL

    NiMc_4245981

      I have a CYPD3120 that resets 10 ms after I turn the sink FETs on.  Is there some DPM condition that needs to be met in that time period? 

       

      Below is an oscilloscope image of the issue.  VBUS (yellow) is a steady 5 V when the sink FETs are enabled.  The output of the FETs (blue) drops after 10 ms due to the CCG3 resetting.  VSYS (Cyan) is powered from the output of the sink FETs.  I've also shown an intermediate signal, USB_VBUS (magenta), which is similar to the V_SYS Oring rail on the CY4531.

       

      CCG3Reset.png

       

      To eliminate the possibility of software causing the reset, I've replaced the call to sink_fet_on with the 4 lines below.  This did not change the oscilloscope plot.

       

      CyGlobalIntDisable;

      sink_fet_on(port);

      CyDelay(15);

      CyGlobalIntEnable;