how to transfer a value from c to a verilog component

[RiRo_4612081]

Hello all,

I'm trying to make a simple component a down counter with 8Bits output counts. During runtime, the period value will be calculated.

The counter works, but I can't set the period value. If I try to implement this I got this error:

Invalid connections at "Net_30849_7" for preset "Net_30849_7S" and reset "Net_30849_7R".

times six with different net numbers.

So my question is could somebody show us(there are several questions in this community about register access in Verilog) a step by step tutorial for how to get a value from c to Verilog.

Attached is my attempt with error it would be nice if someone could explain to me my mistake.

I also tried it with a UDB approach, but it uses the PI PO example I struggle to implement the logic(Reset and counting the counter value and not always adding to PI), but I have the 8Bit input and 8Bit Output. (https://www.cypress.com/file/41531/download). And if I use the Counter/PWM example as a start, I don't accomplish the 8Bit output, but the logic works.

please don't refer me to the DDS24 example. (DDS24: 24-bit DDS arbitrary frequency generator component ) I tried to extract the API access, but I couldn't get it running/ understand it. For me, it looks that he uses the register only to control the states and not the values.

I appreciate your help and Merry Chrismas.

Nachricht geändert durch Richy Ronald Change of reg to wire (periodValue)

[RodolfoGL]

Try to set the periodValue as wire. You don't need to have a second 8-bit register. The control register itself already stores the period for you.

If you are good with 7-bit counter, you can actually use the 7-bit counter primitive as well, it doesn't burn any macrocells.

[RiRo_4612081]

Thanks for your fast response.

unfortunately, the change of the period Value in wire doesn't affect the error.

I tried the seven-bit counter with an offset Bit(LSB) in the Bus which is working. But the reset sets the counter value to 0 ( I connected it to the DAC. Hence i got also 0V for one cycle what I don't want) if I use the load (sync.) it's out of phase/period to the original signal because they have a different frequency.

[RiRo_4612081]

please correct me if something is wrong in my thinking.

Step 1: write Verilog code

module Count8Bit_v1_0 (

    output reg [7:0] count,

    ...);

    wire [7:0] periodValue; // Change to wire

...

always @ (posedge clk or posedge reset)

     begin

         if(reset)

             begin

                 count <= periodValue; // periodValue should be set in code

  ....

Step 2: make instanciation of Register

// connect code reg periodValue_Reg ->  verilog wire periodValue

    cy_psoc3_control #(.cy_init_value (8'hFF), .cy_force_order(`TRUE))  // default mode

   periodValue_Reg(

        .control(periodValue));                                     // periodValue bits [07:00]

Step 3: Add Header file:

     #define `$INSTANCE_NAME`_Control_Reg   (*(reg8 *) `$INSTANCE_NAME`_periodValue_Reg__CONTROL_REG)

Step 4: use in C code with

     Count8Bit_1_Control_Reg = myPeriodVlaue_in_C;

[odissey1 · Accepted solution]

RiRo,

Attached is basic example of instantiating 8-bit Control and Status register inside a custom component (Verilog), and using API to write/read those registers.

/odissey1

[RiRo_4612081]

Thank you very much, BoTa_264741, for your help!

If I modify your project to an 8Bit downward counter with a change period value which I can set in C. Reload to period value is if the counter value is equal to 0. This code works accordingly.

Now I wanted to make the reload (counter value <= periodValue) by an asynchrony reset.

Error: Invalid connections at "Net_30849_7" for preset "Net_30849_7S" and reset "Net_30849_7R".

If I replace the periodValue (wire type assigned with StatusReg) to a fixed value, I don't get an error, but I can't set the variable (reg).

could you please have a look? (Component: SlopeCompensation in the attached project)

[RodolfoGL]

You should avoid to use any asynchronous logic when designing with UDBs. If you remove the "or posedge reset" in the always@ block, the problem will go away.

The UDBs were designed to run everything synchronous to the input clock.

[odissey1]

ReRo,

Unused libraries were removed from the workspace and dependencies. Components were updated (check out orange shield in the bottom). The component was renamed component form "..._V1_0" to "..._v1_0".  The references to the Status register in verilog, *.h / *.c files were commented out, it is useless, as it carries the value from the Control Register. The Control Reg  was changed to Sync Mode and hooked to the reset signal. This makes PeriodValue available to the counter only on reset. Reset was changed to synchronous in *.v. Note that original value of the PeriodValue on counter startup is 0. So the bus output will stay 0 until the counter is reset. Archive is attached.

Finally, can an up- counter be used instead? The implementation is simpler. The reason is that WARP Verilog has no "initial" instruction, so that the counter is initialized to 0 by default.

/odissey1