8 Replies Latest reply on Dec 18, 2019 3:58 AM by JayakrishnaT_76

    SlaveFifo Write Sequence

    GiSa_4520796

      Hi,

       

      I am trying to write to the Slavefifo which is then read by FX3.I am following the timing diagrams as per AN65974 Application Note.But in logic analyzer,the signals are not triggering and coming as attached.Why the signals are not triggering?

       

      Regards,

      Srujana.

        • 1. Re: SlaveFifo Write Sequence
          JayakrishnaT_76

          Hello,

           

          All signals other than Flags are to be asserted by FPGA. Please refer to section 11.4 of AN65974. This describes the implementation on FPGA side.

           

          Best Regards,

          Jayakrishna

          • 2. Re: SlaveFifo Write Sequence
            GiSa_4520796

            Hi,

             

            I am getting both flags (A&B) high before programming FX3 and after programming i am getting FLAGA as 1 and FLAGB as 0.

            But i studied that in order to write data into Slavefifo both flags should be high.But i am getting  FLAGB as 0.Why?

             

            Regards,

            Srujana.

            • 3. Re: SlaveFifo Write Sequence
              JayakrishnaT_76

              Hello,

               

              According to my understanding you are using SlaveFIFO project from AN65974. Please let me know whether you have made any modifications on this. Also, please let me know the value of address lines that you are asserting from the FPGA to select the threads on GPIF II block.

              Also please share the interface timings.

               

              Best Regards,

              Jayakrishna 

              • 4. Re: SlaveFifo Write Sequence
                GiSa_4520796

                Hi,

                 

                I am using default  GpifToUsb firmware which is  modified to work for P-Port to S0-Port.

                 

                please let me know the value of address lines that you are asserting from the FPGA to select the threads on GPIF II block.

                     I am asserting address 0 from the FPGA .

                 

                please share the interface timings.

                 

                Now i am getting both flags as 1,but fx3 side producer events are not generating

                     1.PNG

                 

                 

                 

                     2.PNG

                Regards,

                Srujana.

                • 5. Re: SlaveFifo Write Sequence
                  JayakrishnaT_76

                  Hello,

                   

                  Please use the example project provided along with AN65974 for implementing write to slave fifo. This is because the state machine on GPIF side is different for gpif2usb example and the slavefifo example project.

                   

                  Best Regards,

                  Jayakrishna

                  • 6. Re: SlaveFifo Write Sequence
                    GiSa_4520796

                    Hi,

                     

                    Thanks for your suggestion.Now i will try with example project provided along with AN65974 for implementing write operation.

                    And my question is in example project the dma callback is from P to U but for my application i want it for P to S0.Is there any way of using it for P to S0 without creating another DMA Channel.

                     

                    Regards,

                    Srujana.

                    • 7. Re: SlaveFifo Write Sequence
                      GiSa_4520796

                      Hi,

                       

                      I tried with the example project provided along with AN65974 for implementing write to slave fifo without any modifications.But,after programming the device is not enumerating.Why?

                       

                      Regards,

                      Srujana.

                       

                       

                      • 8. Re: SlaveFifo Write Sequence
                        JayakrishnaT_76

                        Hello,

                         

                        The example project provided along with AN65974 should enumerate properly if you have not made any modifications. I have tested this on my end.

                         

                        Please read the documents Getting Started with FX3 SDK and FX3 SDK trouble shooting guide which comes along with FX3 SDK and can be found in the following location.

                        C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc\firmware

                         

                        Once this is done, please read and understand AN65974 completely. Please note that there is a state machine that is running on the GPIF II side apart from the state machine that works on the FPGA. The GPIF II state machine is provided along with the AN65974 project. The master state machine (FPGA) should match with the state machine on the GPIF II side so that the data is written or read from FX3.

                         

                        For enumeration related queries please go through the following KBA

                        Trouble Shooting Guide for the FX3/FX3S/CX3 Enumeration - KBA222372

                         

                         

                        Best Regards,

                        Jayakrishna