Please refer to the appnote : https://www.cypress.com/file/124206/download
This refers to the designing of a GPIF II Master interface.
You will have to make sure that the master follows the timing diagrams of READ and WRITE as given in the Appnote strictly inorder for your application to work as expected.
You can view the assertion and de-assertion of the signals from FPGA using a logic analyser physically but currently there is no way to check that the data is sent from FPGA to GPIF II using firmware.
Also, to get a better understanding of the timing diagrams to be followed, you can use FX3's in back to back configuration and use one as slave and the other as master and use the slavefifo example and visualize it using a logic analyser to understand the flags and see when they are asserted.