1 Reply Latest reply on Dec 15, 2019 10:58 PM by YashwantK_46

    FPGA to FX3

    GiSa_4520796

      Hi,

       

      My application is to receive data from FPGA i.e...,

       

      FPGA --->GPIF -----> FX3 P-Port ----> S0 Port

       

      I am using GpifToUsb firmware which is modified to work for P-Port to S0-Port.

      My doubt is how to make sure that data is sent from FPGA to GPIF interface.I am checking producer and consumer events in DMA callback(FX3) .

      Is there any way to check from FPGA side that data is transferred to FX3.And also how monitor flags data from FX3 side?

       

      Regards,

      Srujana.

        • 1. Re: FPGA to FX3
          YashwantK_46

          Hello Srujana,


          Please refer to the appnote : https://www.cypress.com/file/124206/download

          This refers to the designing of a GPIF II Master interface.


          You will have to make sure that the master follows the timing diagrams of READ and WRITE as given in the Appnote strictly inorder for your application to work as expected.

           

          You can view the assertion and de-assertion of the signals from FPGA using a logic analyser physically but currently there is no way to check that the data is sent from FPGA to GPIF II using firmware.


          Also, to get a better understanding of the timing diagrams to be followed, you can use FX3's in back to back configuration and use one as slave and the other as master and use the slavefifo example and visualize it using a logic analyser to understand the flags and see when they are asserted.


          You will also need to go through the state machines of both the appnotes AN87216 and AN65974.

           

          Regards,
          Yashwant