Please see below inline
We have designed a hardware prototype that includes a S25FL127S Flash purely for storage (no XIP required) purpose.
The host MCU is Renesas Synergy S7G2. This MCU has support for QSPI.
Accordingly, we have connected all pins required for QSPI with the host MCU. The IO2 and IO3 pins that server alternate purpose of WP# and HOLD have been pulled up using an external 10K resistors.
It is not necessary to have pull-up resistors on IO2 and IO3 pins, as you are using them as I/O pins. And these two pins have week pull-up inside the flash chip if they are not used and left unconnected.
I can successfully read manufacturer ID (01h), type of memory interface (20h) and memory density (18h).
I have been trying for getting the flash operations functional but I can only read all 0xFF. The support from host MCU vendor has indicated that the initialization sequence could be a problem.
If the host is working at Quad I/O mode and expecting data on all 4 pins. Configuration Register-1 bit1 (CR1) must be set to 1 and use Quad output commands or Quad I/O commands.
CR1 default value is 0. Please note:
- this bit is non-volatile bit. It has the same life span as flash array. So don’t write it too frequently, i.e., write it on every power up or reset is a bad practice.
- Use read-modify-write approach to write registers, i.e., read the flash Status Register-1 and Configuration Register-1 into RAM, only update the bits need to be changed, then write back to flash registers
- WRR command supports 8-bit (modify SR1), and 16-bit (modify CR1 or both SR1 & CR1). However once Quad mode is set (CR1=1), WRR can only be used with 16-bit, even only modify SR1, otherwise, QUAD mode (CR1) might be reset to 0
Is there a simpler way of knowing what all actions are required to initialize the chip and what values are to be set up in Status Register 1, Status Register 2 and Configuration Register 1 to support QSPI mode?
QUAD mode bit (CR1) is the only register bit needs to be set to support QSPI mode. However, to correctly read output data, latency code in CR1 also need to be set depends on read mode and clock frequency. Please refer to the Latency Code for the detail value in the datasheet.
Another question: When I intend to use QSPI interface for flash Read, Erase and Page Program operations, what commands should I use out of the below?
(Taken from Section 11.1, page 113, S25FL127S Datasheet):
In QUAD mode, all command code sent to flash is still on SI only. For Quad Output command, command code and address are sent to flash on SI only, flash output data are on all 4 pins. For Quad I/O mode, command code is sent to flash on SI only, address bits are sent to flash on all 4 pins, and flash output data on all the 4 pins.
In QUAD mode, all the commands below still work. But if want to use Quad Output or Quad I/O, then the respective commands need to be used. E.g., Quad I/O Read, Quad Page Program. The 3- or 4-byte address commands are not QUAD mode relevant. As 3-byte address can only access 128Mb (16MB) address space, 4-byte address commands are used to access the address space beyond 128Mb.
- (03h) Read (3-byte Address)
- (13h) Read (4-byte Address)
- (ECh) Quad I/O Read (4-byte Address)
- (20h) Parameter 4 kB-sector Erase (3- or 4-byte address)
- (21h) Parameter 4 kB-sector Erase (4-byte address)
For Page Program:
- (02h) Page Program (3- or 4-byte address)
- (12h) Page Program (4-byte address)
- (32h) Quad Page Program (3- or 4-byte address)
- (34h) Quad Page Program (4-byte address)
- (38h) Quad Page Program (3- or 4-byte address)
I tried the changes you suggested, still reads all 0xFFs. Is there possibility to interface this chip with the conventional SPI mode by selecting Single or Dual mode in pin configuration? If yes, what all changes in initialization process? What happens to Write Protect and HOLD pins?
S25FL127S default works at conventional SPI mode. It can be configured to work at Dual/Quad/QPI mode by setting relevant register bits. The different working modes are not configured through pin configuration.
Can you please provide Logic Analyzer traces for this test, so we can investigate what is really going on?
Happy New Year!
Thank you and Regards,
Thank you for your support. I have managed to get the flash functional by disabling the XIP mode. For our application XIP mode is not required. I am not sure what was the issue with XIP mode, but I'll get into that later.