1 Reply Latest reply on Dec 16, 2019 1:20 AM by EktaN_26

    PSoC62 ILO vs PILO


      I am using ILO and in some boards I see the error greater than 15%.  I cannot find the cause of the problem on my boards and most of the boards don't have this problem.  I am considering switching to PILO.  What are the disadvantages of using PILO over ILO besides higher current of 1.2uA vs 0.3 uA?  I am not using a HF crystal to trim the PILO with.  What will be the accuracy range of PILO if I never trim it?  I am not trimming the ILO either.  Should I be doing this and how often should I do it?  Is there an example project for doing trimming?  I only want an accuracy of 10% like the spec states for ILO but I want to see if I can recover bad boards with > 15% error.

        • 1. Re: PSoC62 ILO vs PILO

          Hello Jefferson,


          PILO has an accuracy of ±2 percent, which can be calibrated to ±250 ppm with a high-accuracy clock source. Since you want an accuracy of only 10%, I would recommend you to use PILO directly without trimming. Please let me know if you are facing any issues when using PILO.


          At present we do not have a code example for doing trimming. But you can refer to the PILO section of Cypress PDL for more details on the usage of the trim function for PILO.


          The disadvantage of using PILO over ILO apart from the current consumption being higher is that PILO is not available in hibernate mode.

          If you are using RTC Timers/ counters in your project then using PILO as source for CLK_LF may lead to corruption of the RTC Timers and Counters.


          Best Regards


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