10 Replies Latest reply on Dec 11, 2019 6:34 AM by RakshithM_16

    Signal Generator in PSoC 6 info

    ClMe_4503246

      Hi everyone!

       

      I have to generate a Chirp signal in my PSoC 6 BLE Prototyping kit.

      Can I use the NOP instruction in the for loop to change frequency?

      Or is there a component to tune the frequency?

        • 1. Re: Signal Generator in PSoC 6 info
          RakshithM_16

          Hi ClMe_4503246,

           

          Please share the following details so that we can help you with your query.

           

          1. The type of signal that is to be generated.

          2. The frequency of that signal.

          3. Please share more details regarding your application.

           

          Thanks and Regards,

          Rakshith M B

          • 2. Re: Signal Generator in PSoC 6 info
            ClMe_4503246

            Hi,

             

            I want to generate a Chirp signal that goes from 38 kHz to 42 kHz in 5 ms to drive a sonar sensor using my PSoC 6 BLE Prototyping kit.

            My problem is that the resolution of CyDelayUs instruction it's not enough cause I want a slower variation.

            What else can I do?

            I was thinking of using a PWM Block and change the value of period0 and compare0 with a for cycle:

             

                        for(uint32 j =0; j<31; j++)

                        {  

                            PWM_1_Start();

                           

                            uint32 period_start = Cy_TCPWM_PWM_GetPeriod0(TCPWM0, MY_TCPWM_PWM_NUM);

                            uint32 period= period_start - j;

                            uint32 compare= period/2;

                          

                            for(int i = 0; i<6; i++)

                            {

                                Cy_TCPWM_PWM_SetPeriod0(TCPWM0, MY_TCPWM_PWM_NUM, period);

                                Cy_TCPWM_PWM_SetCompare0(TCPWM0, MY_TCPWM_PWM_NUM, compare);

                            }

                        }

             

            but it doesn't work!

             

            Thank you!

            CM

             
            • 3. Re: Signal Generator in PSoC 6 info
              RakshithM_16

              Hi ClMe_4503246,

               

              I was able to generate a signal which goes from 38 kHz to 42 kHz in 5 ms. I have shared the screenshots of my measurements for your reference.

               

              Figure 1 - Total time = 5 ms

              Figure 2 - Starting frequency = 38 kHz

              Figure 3 - Ending frequency = 42 kHz

              I have also attached the project. Please let me know if this works for you.

               

              Thanks and Regards,

              Rakshith M B

              • 4. Re: Signal Generator in PSoC 6 info
                BoBr_4596421

                Wow!

                Rakshith, this is awesome!

                 

                I hope you both don't mind me popping my head in here, but I am finding this a helpful learning resource.

                I got a lot of what you did Rakshith, but I missed a lot too.  I'm unclear on how to take your zip file and read it in my system - do I simply unzip and add the folder into my workspace or will that corrupt a database somewhere in PSoC Creator? I guess if I do this, that will answer a lot of my questions.

                 

                It may be too much to ask (and if so, that's fine!), but if you had the time I would really appreciate a few paragraphs of text giving an overview on the strategy of how you went about this design solution.

                 

                Some specific queries (and apologies if they can be pretty basic:-

                1) I'm unclear what data type is being used in 'Cy_TCPWM_PWM_SetCompare0'. I suspect it may be a uint32 like the related GetCompare0? If that's correct then every second iteration through the 'for' loop (odd values of 'i') may be rounding the expression '(period0 - i)/2)'  and I wondered if this may be introducing unwanted jitter in the output?

                2) I couldn't find any reference to the clock frequency setting in the files? This is presumably set in the design schematic and then not touched by the program?

                3) In 'main_cm4.c' you use the output pin TEST. Where in the code does this selection get put? I guessed 'cyfitter_gpio.h' as this was the only file I could find with 'gpio' in the title, but it's not there. As above, I expect that this got set in the design schematic but I'm curious on where it ends up in the code.

                4) Is the file PWM.c auto-generated or hand-created? 

                4a) I don't believe you are using swap mode on the PWM - is that correct?

                4b) I'm using the CYBLE-416045-02 EZ-BLE prototype board and all the parameters you have set in 'PWM_config' to a value of '3UL' look like they need to be set to '7UL' in my system as the selectable options are 0, 1, 2, or 7??  (These may be seen by double-clicking on the PWM device in the design schematic and then seeing the values for each selection in the right-hand panel.

                 

                Regards

                Bob

                • 5. Re: Signal Generator in PSoC 6 info
                  RakshithM_16

                  Hi BoBr_4596421,

                   

                  I'm unclear on how to take your zip file and read it in my system - do I simply unzip and add the folder into my workspace or will that corrupt a database somewhere in PSoC Creator?

                  Yes, if you just extract the archive file and open the project file (with extension .cyprj) with PSoC Creator then you will be able to use the project.

                   

                  I would really appreciate a few paragraphs of text giving an overview on the strategy of how you went about this design solution.

                  1.  So the output should start with 38 kHz and go up till 42 kHz. So the period of the signal needs to change from 26.3 us to 23.8 us. This change should be observed in 5 ms. Therefore, CyDelayUs() function cannot be used as mentioned by ClMe_4503246.

                  2.  The next option is to use a PWM output and change its period from 26.3 us till 23.8 us. PWM period can be changed during run-time.

                  3.  Next step is to decide the PWM configuration. Choosing a 1 MHz clock will again result in the same issue that we were facing with CyDelayUs() API. So I set the clock frequency to 10 MHz. Now in the code, when i = 0, the period is set to 262 which will output a 38 kHz (approx) signal. The compare value is always period/2 to make sure that the signal has 50% Duty cycle.

                  4.  The period value should be decreased from 262 to 238, so a total of 25 period changes (including the initial set-up). This should be done in 5 ms. So after each period change there needs to be a delay of 5000/25 = 200 us.

                  5.  After the PWM output reaches I am disabling the PWM component.

                  6.  For debug purposes, I used a Test pin which is set to 1 before the PWM period is changed and the Test pin is set to 0 once the PWM component is disabled.

                   

                  1) I'm unclear what data type is being used in 'Cy_TCPWM_PWM_SetCompare0'. I suspect it may be a uint32 like the related GetCompare0? If that's correct then every second iteration through the 'for' loop (odd values of 'i') may be rounding the expression '(period0 - i)/2)'  and I wondered if this may be introducing unwanted jitter in the output?

                  Excellent observation BoBr_4596421. Yes, Cy_TCPWM_PWM_SetCompare0() takes a uint32 compare value. You can check this by right clicking on the function and clicking on Go To Definition. To answer your question, you are correct, the compare value will be rounded off. I was not sure of the rate at which the signal frequency should increase. This can be avoided by decrementing the period value by 2 and increasing the delay value from 200 to 400.

                   

                  2) I couldn't find any reference to the clock frequency setting in the files? This is presumably set in the design schematic and then not touched by the program?

                  Right, clock is set in the TopDesign.

                   

                  3) In 'main_cm4.c' you use the output pin TEST. Where in the code does this selection get put? I guessed 'cyfitter_gpio.h' as this was the only file I could find with 'gpio' in the title, but it's not there. As above, I expect that this got set in the design schematic but I'm curious on where it ends up in the code.

                  I am sorry but I did not understand your question. I used a digital output pin in TopDesign and if you build the project or click on Generate Application this will create the macros that is needed by the API. The macros are generated in the cyfitter_gpio.h file.

                   

                  4) Is the file PWM.c auto-generated or hand-created? 

                  4a) I don't believe you are using swap mode on the PWM - is that correct?

                  4b) I'm using the CYBLE-416045-02 EZ-BLE prototype board and all the parameters you have set in 'PWM_config' to a value of '3UL' look like they need to be set to '7UL' in my system as the selectable options are 0, 1, 2, or 7??  (These may be seen by double-clicking on the PWM device in the design schematic and then seeing the values for each selection in the right-hand panel.

                  Yes, PWM.c is auto-generated. In fact, all the files in Generated_Source folder is auto-generated.

                  I am not using the swap mode on the PWM.

                  CYBLE-416045-02 EZ-BLE uses a PSoC 63 chip. So I selected a PSoC 63 chip in the device selector and I built the project. Input mode values are still set to 3UL. As these files are auto generated, when you select your device and build the project, these values will be auto filled. The inputMode value is still 7 for me -

                   

                  Hope this helps,

                   

                  Regards,

                  Rakshith M B

                  • 6. Re: Signal Generator in PSoC 6 info
                    BoBr_4596421

                    Rakshith, Hi

                    An excellent answer thank you. This is helping me a lot.

                    Now that I better understand, possibly another solution to generating the 5mS gate could be to have two PWMs with the first being the clock for the second and set to a 5mS pulse. This would gate the high frequency tone.

                     

                    Regards

                    Bob

                    • 7. Re: Signal Generator in PSoC 6 info
                      RakshithM_16

                      Hi BoBr_4596421,

                       

                      I am sorry but I am not able to understand your application. According to my understanding you are using a PWM to generate a 5 ms pulse.

                      the first being the clock for the second and set to a 5mS pulse. This would gate the high frequency tone.

                      I fail to understand this statement.

                      Can you please elaborate your idea?

                       

                      Thanks and Regards,

                      Rakshith M B

                      • 8. Re: Signal Generator in PSoC 6 info
                        BoBr_4596421

                        Apologies Rakshith, it was a poorly expressed idea.

                         

                        My thought was to use two x PWM, one for the 'high' frequency and one acting as a gate. However the way to achieve that was incorrectly stated as simply using one to 'clock' the other would not work. Do you think it possible to use the 5ms PWM to 'enable' the other in hardware? I haven't yet explored the Smart I/O block - is it possible to program this to operate as an 'AND' function?

                         

                        Regards

                        Bob

                        • 9. Re: Signal Generator in PSoC 6 info
                          ClMe_4503246

                           

                          • 10. Re: Signal Generator in PSoC 6 info
                            RakshithM_16

                            Hi,

                             

                            BoBr_4596421, start and kill inputs of the PWM can be used to enable the PWM at the rising edge of the signal and disabling it at the falling edge of the signal. But, the PWM period has to anyway be changed in firmware. So, there might be issue in synchronizing the 2 PWM outputs which needs to be taken care. For example - the first PWM might disable the second PWM before the output reaches 42 kHz.

                             

                            ClMe_4503246, can you please make sure that the sensor will work with digital output? The sensor might require a Chirp signal similar to the one described in this link.

                             

                            The steps to create a similar chirp signal -

                            1. Generate sample points of the chirp signal (probably using MATLAB).

                            2. Store the sample point values in a buffer.

                            3. Use DMA to write the buffer values into the DAC to generate the output.

                             

                            Thanks and Regards,

                            Rakshith M B