13 Replies Latest reply on Dec 17, 2019 7:39 PM by JayakrishnaT_76

    fx3 application

    thko_4554996

      I am trying to create a fx3 slave application with a full and empty flag that is used with an fpga. The fpga assumes the role of master. I programmed the fx3 with the cypress slavefifosync example. However, I don't see any full or empty behavior that I would expect to see based on the user guide timing diagram. The  fx3 example project has 4 flags one of which goes high when I write test data to the endpoint using the usb control center application. The flag never goes low even though I am reading the fifo through a gpif interface from my fpga. What am I missing? Are the full and empty flags even part of the slavefifosync example?

        • 1. Re: fx3 application
          JayakrishnaT_76

          Hello,

           

          Please let me know how many bytes you transferred to the USB Port using the Control Center Application. Also, did you read the transferred data completely using FPGA?

          The full and empty flags are a part of slavefifosync example. They signal the availability of data for read operation or availability of space for write operation in the FIFO. For read operation from the FIFO, the flag is de-asserted (that is remains in HIGH state) until the FIFO is empty. Once the FIFO is empty, the flag is asserted (goes to low state). For write operation to the FIFO, the flag is de-asserted (remains in HIGH state) until the FIFO is full. Once the FIFO is full, the flag is asserted (goes to low state).

           

          Best Regards,

          Jayakrishna

          • 2. Re: fx3 application
            thko_4554996

            Hello Jayakrishna,

            I have tried to send two, two byte transfers  The third 2 byte transfer fails with error code 997. I suspect that I am not successfully removing data out of the read fifo of the fx3 from the fpga side. I am trying to insert a logic analyzer core into the fpga now and will let you know what I find.

            thanks,

            Thane

            • 3. Re: fx3 application
              JayakrishnaT_76

              Hello,

               

              The example project in FX3 SDK makes use of 2 DMA buffers in U to P channel. If you are sending data two times through the control center application and not reading data from the P Port, then you will see this error if you attempt to send data 3rd time. Please check whether you are reading data at the P Port and let me know the result.

               

              Best Regards,

              Jayakrishna

              • 4. Re: fx3 application
                thko_4554996

                Hello Jayakrishna,

                Here is a screen shot from my logic analyzer core in the fpga. When I send 2 bytes the empty appears to deassert as expected but never gets reasserted after my read attempt. what am I missing here?

                Thane

                • 5. Re: fx3 application
                  JayakrishnaT_76

                  Hello Thane,

                   

                  For the read operation from the Slave FIFO to be successful, the master should meet the timings as described in section 5.1 and 5.2 of the Application Note AN65974. The link to the application note is given below:

                  https://www.cypress.com/file/136056/download

                   

                  Please let me know which is the signal from FPGA that is used for selecting the thread/socket of P Port of FX3. Also, please provide the capture from the logic analyzer with the interface clock so that I can compare it with other signals.

                   

                  Best Regards,

                  Jayakrishna

                  • 6. Re: fx3 application
                    thko_4554996

                    hello Jayakrishna,

                    I thought the address lines selected the thread/socket. In my case the address lines are fx3_addr.  Please let me know if this is not how to select the thread/socket of the p port. I followed the timing outlined in an68829 slave fifo interface for fx3 document and the technical ref guide. I will try to send you another logic analyzer screen shot with the clock.

                    thanks,

                    Thane

                    • 7. Re: fx3 application
                      thko_4554996

                      I am still not seeing any data come back from the cypress part. I am running the slavefifo example code on the part and have tried may things to read data out of it with no success. I see the empty (flagc ) go high and then never go low until I reset the end point. I never see data presented on the bus. I have tried holding cs,rd,and oe low and just watching data on the bus. The data goes from ffff to 0000 and the empty never goes low. I am trying to read from address 3 which should be thread 3 socket 3. I am using the usbg control center to send data to endpoint 0x01. What am I missing. This is holding up our product develpment cycle. I have also verified the clock and control signals at the pins of the fx3. clock is good, signals are changing as expect from the fpga. I really need to get this resolved asap!!!!!!!!!!

                      • 8. Re: fx3 application
                        thko_4554996

                        I am using the AN65974 SlaveFifoSync project without any modifications. Is there something that needs to change in the project to get data in and out of the part?

                        • 9. Re: fx3 application
                          JayakrishnaT_76

                          Hello,

                           

                          I apologize for the late reply but I was waiting for the logic analyzer screenshot with the clock. Your understanding regarding address lines is correct. They are used to select the thread/socket. Please confirm which timing diagram you are implementing on FPGA? Is it the one in AN68829 or in AN65974. Please try using the timing diagrams in AN65974.

                          Also, please let me know if you are receiving any of the data sent from the USB side on the FPGA. You had mentioned in your previous reply that the data goes from ffff to 0000 so did you transmit 0000?

                          Also, please let me know the status of partial flag.

                           

                          Best Regards,

                          Jayakrishna

                          • 10. Re: fx3 application
                            thko_4554996

                            Hi Jayakrishna,

                            Sorry about not adding the clock in the logic analyzer screen shot. I have been unable to get the clock signal into the logic analyzer because the logic analyzer chipscope instance uses the clock to run. I modified the design to just pull the read select line down( and oe low) and hold it there and at the same time registering data coming across the gpif interface every clock. No data comes back. I do see the lines drop from ffff to 0000 when the empty flag goes high. However I am not sending ffff or 0000 to the fpga. I have sent 2 bytes of data at a time, 1024 bytes through a file transfer and a host of other scenarios. I am using AN65974 timing diagrams since the design is a 2 address line design. The partial status flag (flag d) remains low. I have seen partial empty (flag d) transition from low to high to low with the last transition to low happening at the same time the emtpy flag goes high. It seems like I am just unable to empty the fifo on the fx3 side. Do the buffers have to be full in order to present data onto the gpif bus? Am I not using the usb control center properly? I have been able to run the debugger through eclipse on the slave fifo project but I am hoping I don't have to debug the code. what could be preventing the fx3 from driving data out onto the gpif bus?

                            Thane

                             

                            • 11. Re: fx3 application
                              JayakrishnaT_76

                              Hello,

                               

                              Please go through my following comments:

                              1. Confirm whether you are using the example project slavefifosync in the FX3 SDK or the project that comes along with AN65974.

                              2. Confirm whether you are receiving prod_events for the DMA channel between U to P Port. This can be verified by putting a CyU3PDeviceReset(CyFalse); in the DMA callback function for the U to P channel.

                              3. Confirm whether the CyU3PDmaChannelCommitBuffer API is failing in the same callback as mentioned above.

                               

                              You can see that the PROD_EVENT will be triggered even when you send 2 bytes of data through the control center. If 2 and 3 mentioned above are met properly, then the data will be transferred to P Port. Now you need to configure the FPGA properly to read data from the Buffer. Please make sure that the SLOE is asserted before SLRD is asserted as shown in fig 3 of AN65974. Also, the status of partial flag seems fine. It remains low because the watermark value is set to 4. So it will be asserted when the number of data bytes in the  buffer is 4. But you only have 2 bytes, so it will remain low.

                               

                              Best Regards,

                              Jayakrishna

                              • 12. Re: fx3 application
                                thko_4554996

                                Hi Jayakrishna,

                                I got it working! There was a problem with one of the address lines on the board. Thanks for you help. I am driving sloe and slrd on the same clock edge. The timing diagram in figure 3 of AN65974 shows sloe going low about a half cycle before slrd. Still both are driven low before the rising edge of the next pclk cycle. This is how I have implemented the control on the FPGA side and it seems to work fine. Should I be worried? I have been able to read and write to the fpga through the usb control center.

                                Thane

                                • 13. Re: fx3 application
                                  JayakrishnaT_76

                                  Hello,

                                   

                                  Sorry for the mistake. I also find that SLOE and SLRD are sampled at the same clock edge by the FX3. So it will not be a problem. Thanks for the update.

                                   

                                  Best Regards,

                                  Jayakrishna