6 Replies Latest reply on Dec 6, 2019 9:40 AM by thko_4554996

    fx3 application

    thko_4554996

      I am trying to create a fx3 slave application with a full and empty flag that is used with an fpga. The fpga assumes the role of master. I programmed the fx3 with the cypress slavefifosync example. However, I don't see any full or empty behavior that I would expect to see based on the user guide timing diagram. The  fx3 example project has 4 flags one of which goes high when I write test data to the endpoint using the usb control center application. The flag never goes low even though I am reading the fifo through a gpif interface from my fpga. What am I missing? Are the full and empty flags even part of the slavefifosync example?

        • 1. Re: fx3 application
          JayakrishnaT_76

          Hello,

           

          Please let me know how many bytes you transferred to the USB Port using the Control Center Application. Also, did you read the transferred data completely using FPGA?

          The full and empty flags are a part of slavefifosync example. They signal the availability of data for read operation or availability of space for write operation in the FIFO. For read operation from the FIFO, the flag is de-asserted (that is remains in HIGH state) until the FIFO is empty. Once the FIFO is empty, the flag is asserted (goes to low state). For write operation to the FIFO, the flag is de-asserted (remains in HIGH state) until the FIFO is full. Once the FIFO is full, the flag is asserted (goes to low state).

           

          Best Regards,

          Jayakrishna

          • 2. Re: fx3 application
            thko_4554996

            Hello Jayakrishna,

            I have tried to send two, two byte transfers  The third 2 byte transfer fails with error code 997. I suspect that I am not successfully removing data out of the read fifo of the fx3 from the fpga side. I am trying to insert a logic analyzer core into the fpga now and will let you know what I find.

            thanks,

            Thane

            • 3. Re: fx3 application
              JayakrishnaT_76

              Hello,

               

              The example project in FX3 SDK makes use of 2 DMA buffers in U to P channel. If you are sending data two times through the control center application and not reading data from the P Port, then you will see this error if you attempt to send data 3rd time. Please check whether you are reading data at the P Port and let me know the result.

               

              Best Regards,

              Jayakrishna

              • 4. Re: fx3 application
                thko_4554996

                Hello Jayakrishna,

                Here is a screen shot from my logic analyzer core in the fpga. When I send 2 bytes the empty appears to deassert as expected but never gets reasserted after my read attempt. what am I missing here?

                Thane

                • 5. Re: fx3 application
                  JayakrishnaT_76

                  Hello Thane,

                   

                  For the read operation from the Slave FIFO to be successful, the master should meet the timings as described in section 5.1 and 5.2 of the Application Note AN65974. The link to the application note is given below:

                  https://www.cypress.com/file/136056/download

                   

                  Please let me know which is the signal from FPGA that is used for selecting the thread/socket of P Port of FX3. Also, please provide the capture from the logic analyzer with the interface clock so that I can compare it with other signals.

                   

                  Best Regards,

                  Jayakrishna

                  • 6. Re: fx3 application
                    thko_4554996

                    hello Jayakrishna,

                    I thought the address lines selected the thread/socket. In my case the address lines are fx3_addr.  Please let me know if this is not how to select the thread/socket of the p port. I followed the timing outlined in an68829 slave fifo interface for fx3 document and the technical ref guide. I will try to send you another logic analyzer screen shot with the clock.

                    thanks,

                    Thane