1 Reply Latest reply on Dec 9, 2019 9:10 PM by VasanthR_91

    Bugfix: synthesis error in GlitchFilter_v2_0

    StSi_284576

      Hi Cypress Team,

       

      there is a small syntax error in the Verilog module of GlitchFilter_v2_0. It is triggered when signal width >1 and "Bypass filter at Logic on/zero" is selected.

      Attached patch will fix this.

       

      Thank you.