8 Replies Latest reply on Dec 2, 2019 5:50 AM by LePo_1062026

    Shiftregister Store interrupt

    user_4564791

      Hey Guys,

       

      I'm relativley new in programming and PSoC. Right now I try to build a little shiftregister but I can't figure out how to read out the value from the output FIFO with an ISR.

      Here is my setup:

      With the two PWMs and the logic 'AND'  I am generating a '1 0 0 0' bit flow every 10 kHZ. In the end I'm curious what is the speed limit from the ShiftReg.

      I want to trigger the interrupt after 8 bits were shifted in. Therefore I connected a 5 kHz clock to the store input and selected 'Use interrupt' and 'on store' in the Shiftreg specification. In the ISR I want to read out the data from the FIFO. The UART component is just to display the output.

      In the Debug mode I can see that the interrupt is only triggered once. Can somebody tell me what I'm doing wrong?

      I already reproduced the example ShiftReg. In this example the load/ store inputs aren't triggered with clocks but with control registers.

       

      Thanks in advance!

        • 1. Re: Shiftregister Store interrupt
          JoMe_264151

          Easiest for us is when you upload a project archivee using advanced editor.

          You probably did not call ShiftReg_GetIntStatus() within the handler to clear the interrupt.

           

          Bob

          • 2. Re: Shiftregister Store interrupt
            user_4564791

            Thank you for your reminder Bob. I uploaded the project. With the "ShiftReg_GetIntStatus()" call the interrupt is working. I thought the "xxx_ClearPending()" statement would clear the interrupt...

            Now I'm wondering why the ShiftReg is only having the values 0x00 or 0xFF.

            • 3. Re: Shiftregister Store interrupt
              LePo_1062026

              user_4564791,

               

              Working on it.  Thanks for uploading your project.

               

              I can answer some of your questions now.

               

               

              In the Debug mode I can see that the interrupt is only triggered once. Can somebody tell me what I'm doing wrong?

               

              I get the same results with your project as is.  When I add the following line in CY_ISR(isr_store_Handler), I get multiple interrupts:

              ShiftReg_1_GetIntStatus();          // This clears the interrupt source to allow new on_store interrupts to occur.
              

               

              Also here a big tip since your new to programming in general:  The goal of an interrupt should always be, to grab the data for the event that caused the interrupt, store it and then exit the interrupt.  In your case, you put UART calls as well as a CyDelay().  The UART calls are potentially a blocking call.  The CyDelay() is ALWAYS a blocking call.  You really never want to stay in an interrupt any longer than you have to.  Staying in an interrupts blocks other interrupts that may be very important to be serviced.

               

              The maximum clock speed of an 8-bit shiftregister is 52MHz.  You're design is nowhere near this limit.

               

              When I got better answers to your operational questions, I'll upload a modified version of your project.

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              • 4. Re: Shiftregister Store interrupt
                LePo_1062026

                user_4564791,

                 

                I believe I have your answer.

                 

                Your design included two PWMs both with a period of 255 and a compare of 127.  This means the PWM toggle occurs every 128 10KHz clocks for PWM_1 and every 128 20KHz clocks for PMW_2.  Your statement:

                With the two PWMs and the logic 'AND'  I am generating a '1 0 0 0' bit flow every 10 KHz."

                is not correct.  This is why you tend to see 0x00 most of the time and 0xFF occasionally.  I received the same results.

                Here is a pic of the new scope plot for your Topdesign.  With the 0b1000 pattern in the AND occurring every 19.20ms.

                 

                I've attached a modified version of your project for your review.  If gets rid of your PWMs and feeds the 10KHz and 20KHz clocks directly into the AND.

                Here is the resultant terminal output:

                Shift value = 0x88  status = 0x02

                Shift value = 0x88  status = 0x02

                Shift value = 0x88  status = 0x02

                Shift value = 0x88  status = 0x02

                The shift value = 0x88 = 0b1000 1000  as you were hoping for.

                 

                Here is a pic of the new scope plot for this design change.

                 

                Len

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                • 5. Re: Shiftregister Store interrupt
                  user_4564791

                  Hey Len,

                   

                  thank you very much for your solution and your general advice for programming! It helped me a lot.

                  Do you have an idea why the output from the ShiftReg depends on the frequencies?

                  I get the following results:

                    

                  clock configuration [kHz]result
                  20 / 10 / 5 / 2.5 0x88
                  40 / 20 / 10 / 50x88
                  200 / 100 / 50 / 250x0F
                  1000 / 500 / 250 / 1250x03C

                   

                  Maybe with higher frequencies the  clocks aren't synchronous anymore? Or is the ShiftReg not working properly with higher frequencies? But I'm still far away from the 52 MHz...

                  Next week I will have my oscilloscope back so I can generate a proper scope plot.

                   

                  Best regards

                   

                  Kurt

                  • 6. Re: Shiftregister Store interrupt
                    LePo_1062026

                    Kurt,

                     

                    I tried your test.  Here's my results

                    clock configuration [kHz]result
                    20 / 10 / 5 / 2.50x88
                    40 / 20 / 10 / 50x88
                    200 / 100 / 50 / 250x88
                    1000 / 500 / 250 / 1250x88

                     

                    No issue.  Are you sure you changed the clock frequencies in the proper order?

                     

                    Len

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                    • 7. Re: Shiftregister Store interrupt
                      user_4564791

                      Hi Len,

                       

                      I am sure that I change the frequencies in the rigth order. Maybe it is due to some warnings I'm getting? I don't understand them but they  appear on every configuration.

                      Tomorrow I can finally measure the different signal paths. I'll let you know if I find out where the different results are coming from.

                      Also very confusing: if I don't use the 8 bit ShiftReg rahter a 16 or 32 bit ShiftReg I get the correct results...

                      • 8. Re: Shiftregister Store interrupt
                        LePo_1062026

                        Kurt,

                         

                        I get the exact same warnings and still get the "correct"  answer.

                         

                        In either case, I'm not sure why it's complaining about a ASync clock since all the clocks used here are sourced from the MASTER_CLK.

                         

                        Len

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