10 Replies Latest reply on Dec 10, 2019 1:43 AM by MaMi_1707981

    [CYBT-343026-01] A2DP I2S configuration (A2DP source, I2S slave) High clock rate

    MaMi_1707981

      Can we use 3.073MHz as I2S clock for "48kHz, 16 bits, 2 channels" ?

       

      The data rate is "48kHz, 16 bits, 2 channels -> 1.536 Mbps".

      So, the clock rate is higher than the data rate.

       

      Can CYBT343026 accept the settings ?

       

      If yes, I think some padding data will be inserted in it.

       

      Is the followings correct ?

          WS: 48kHz

          <Lch(16bit: MSB->LSB), padding(16bit)>,    <Rch(16bit, MSB->LSB), padding(16bit)>,    <Lch, padding>,    <Rch, padding>,  ...