3 Replies Latest reply on Nov 23, 2019 8:49 AM by LePo_1062026

    Loadable Counter

    IvPa_1668871

      Is there an app note showing how to implement loadable counter, please ? E.g. 16 bit down counter where an initial value is set by software.

        • 1. Re: Loadable Counter
          LePo_1062026

          ivpa,

           

          Here's an example project where a random number can be loaded into the counter.  In this example, the timer (used as a counter) counts down once every 10 msecs.  Pretty slow but it allows the terminal update to be readable.  It loads a new random number every time it finishes a countdown.

           

          I've implemented this on a 16-bit timer but for the purposes of this example I only allow 1 to 100 as a random number load.

           

          Len

          • 2. Re: Loadable Counter
            IvPa_1668871

            Thanks for your help.

            I found the solution in AN82156, chapter 6, Project #1 - 8 Bit Down Counter.

            I also realized that I have to go to Verilog in order to finalize my project.

            Is it possible to create a component and then add it to the Cypress Component Catalog in PSoC Creator ?

            I am willing to add the components which I create.

            • 3. Re: Loadable Counter
              LePo_1062026

              IvPa,

               

              Yes.  you can create components and share them with the PSoC community.   I'm not an expert in this matter.  There are others with more experience in Verilog and component creating.  There should be some app notes to help.  I believe there is component authoring information in the Help menu of PSoC Creator.

               

              Len