3 Replies Latest reply on Mar 25, 2020 11:16 PM by RajathB_01

    CCG3 OVP port reset




      We are using the CCG3 CYPD3125-40LQXIT with a custom notebook firmware based on the notebook example of the SDK 3.2.1, and we're having some strange behavior when powered by the USB-C. Our board have a consumer role with a VBUS at 20V. When our board is off, only the CCG3 is powered, from the VBUS. When the board is on, all the board is powered from the USB-C VBUS and the CCG3 is powered from its VSYS. When the board is powered down, the VSYS of the CCG3 is lost and the CCG3 is only powered from the VBUS. At this moment, an over-voltage is detected by the CCG3 and the port is reset. The VBUS is lost and the CCG3 shuts down. This wasn't expected.


      I have probed the VBUS with an oscilloscope and I can't see any over-voltage. The maximum overshoot seems to be 500mV. The OVP Threshold parameter is at 20% in the configuration, so it should not trigger an OVP. I see that there are the "Debounce period" and "Retry count" parameters in the Over Voltage Protection section of the configuration, but these parameters can't be changed for the CCG3. These parameters can't be increased to see if it has an effect.


      Our CCG3 firmware also controls the board power with a GPIO. It shows the same behavior as when the power is removed without interaction of the CCG3 (described above). But, if a delay of 15ms or more is added after toggling this GPIO to power down the board (delay added with the function CyDelay), no over-voltage is detected, the CCG3 switches from VSYS to VBUS and it continues to operate as expected.


      Any ideas of why OVP is triggered in some conditions and not with a delay in CCG3 firwmare? And how could I prevent an OVP when powering down the board?