Can you please share your board schematics and also VBUS waveforms?
I have observed two cases on the VBUS, one with more voltage variation and one with less variation. The VBUS behaves the same way if the CCG3 resets or if it doesn't reset by adding a delay.
Our board schematics are very similar to the DRP Application Diagram example in the datasheet or the CY4531 evaluation kit. I have sent you a direct message with our schematic.
- Schematic review: No problems found
- Attempt at reproducing the issue: Unsuccesful
- Workaround: Existing workaround of delay seems appropriate
- Further investigation: Requires debugging with the actual board sample and firmware
Please open a new thread as discussed in order to avail more support or if you want to update us about anymore issues.