Thank you for contacting Cypress Semiconductor.
I am discussing your case internally, however I would also like to ask you a few questions -
- What is the age of the devices that you are working on? Are the devices very old and is it possible that they may have undergone excess number of program/erase cycles?
- Is the data being programmed in both the devices same? Specifically, the nature and size of data (number of bytes of data) being programmed. The programming rate mentioned in the datasheet is the per page program rate.
1. We tested one flash S25FL256S that was new before we ran the tests. We tested several S25FL256L (not new but they didn't undergone excess number of program/erase cycles) and we obtained roughly the same programming time for each (smaller than with S25FL256S).
2. Yes, the data programmed are exactly the same in both cases.
I checked internally with design team and they have confirmed that the datasheet values are correct as it has been tested on actual silicon before the release.
Could you please answer my below questions -
- Please confirm that nothing is interrupting the program operation in any way.
- Is the flash being used under any extreme conditions (vcc/temperature) ?
- How are you measuring the operation time?
- Could you please provide the SPI waveforms for both FL-L and FL-S parts so that we can verify the timing?
Here are the captured SPI transactions (Write) with the flash FL-S and FL-L :
First test: write transactions of 256 bytes equal to 0
Second test: write transactions of 256 bytes equal to 1
We observe a high variability in the time taken by the flash FL-S between two exact same write transactions. However, the transaction of the flash FL-L are quite steady.
The mean transaction time (over a buffer of 13.061 KB) is higher for the flash FL-S than for the flash FL-L
Do you have an explanation for this ?
Thanks in advance !
Thank you for your reply.
From the wave form provided by you I am assuming you are performing page program operation and then reading the Status Register continuously to make sure that WIP bit has reset to zero indicating successful completion of page program operation. It would be really helpful if you could tell the exact command sequence being followed. However, I have a few questions.
In the first_test_l wave form, can you please explain this gap in the CLK signal (marked in RED) while the CS# is still low? The gap in the CLK is present in all the four test case wave forms.
When the CS# first goes LOW, the device will expect the command, address and data on the MOSI line, however, in the waveform, the MOSI line is staying low throughout (marked in GREEN). Ideally the MOSI line should have toggled according to the command and address provided and stayed low after that, given the fact that the data being programmed is all zeros.
Could you please provide a more clear waveform for a single write operation for each test case? With multiple write operation wave forms in the same window it is difficult to see the toggling of the signals.
I would also like to point out that the time taken by FL-S device in both test cases (456us and 304us) are within the datasheet limits.
Here are the captures with only one transaction for each test:
Here is the order of operation :
- Write enable (appears at the end of the waveforms shown above)
- Polling status register until WIP bit is cleared (appears at the end of the waveforms shown above)
- Page program command (you can see the code 12h in the decoded MOSI signal at the bottom of the captures)
- Polling status register until WIP bit is cleared
- Write Disable
- Polling status register until WIP bit is cleared
I don't know exactly why there is a gap in the CLK signal. We use a Xilinx SPI controler and we don't know in the exact details of how it works. But as this gap is the same for flash L and S, it is not important here.
To come back to my first question, how do you explain a difference of more than 100 microseconds between two exact same page program operations with the flash FL-S ? These page program operation are consecutive and the conditions (temperature, number of cycles) are therefore exactly the same.
The difference appears only during the "Polling status register until WIP bit is cleared" just after the Page program command.
And Is it normal to have a mean programming time greater for flash FL-S than flash FL-L ?
We cannot tell that the programming time for all of the FL-S devices will be faster than the FL-L devices. Because, the timing specifications of our devices will vary depending upon the fabrication process variations of the die. Not all devices manufactured will have the exactly same timing specifications. Before shipping, we test these devices and make sure that the timing parameters are within the min and max limits mentioned in the datasheet.
example: page programming time of FL256L device is between 300us to 1200us. It means, the page programming time of the FL256L devices that we ship, will vary between 300us and 1200us. There will be devices with page programming time 500us, 700us, 650us etc. Same thing applies for FL-S also. Page programming time (256 bytes) of FL-S devices will vary between 340us and 750us.
So, when you compare page programming time of FL-S and FL-L devices, FL-S device will not be always be faster than FL-L device. But, you will never find an FL256S device with page programming time more than 750us (datasheet max limit).
Page programming time can vary depending upon the data pattern also. The operations "Program" means, changing bits from 1 to 0. It cannot change a bit back to 0 from 1. Only and erase operation can change a bit from 0 to 1. So, depending upon the number of '0' bits in the data, the programming time can vary.
I hope the above explanation answers your query. Please let me know, if you need any clarifications.
Thanks and Regards,
Thanks for your answer ! It explains why the programming time of the flash FL256S can be higher than the programming time of the flash FL256L.
I want to come back again to my question on the high variability between same and consecutive page programming commands for the flash FL256S.
We start with an erased page and the three page programming shown below are the same (writing 256 bytes equal to 0) and the address in flash are consecutive also (separated by 256 bytes). So for these three commands, 256 bytes are changed from 1 to 0. However, we observe difference of more than 100 µs between these commands.
Is this considered as a normal behaviour ?
I have a last question: is it possible to have an erase time significantly smaller for the flash FL256S than for FL256L while having a longer programming time ?
Apologies for the delay in my response.
As long as the programming and erase timings are staying within the datasheet specified limits, observing a difference in program/erase time for different memory locations is a normal behavior.