1. Please probe the bus and share the screenshots of the issue your are facing.
2. Send us a project that focuses on the issue so that we can reproduce the issue from our end. This is important to understand your issue and provide a solution. To send the project, refer to Archiving a PSoC Creator Design.
3. Check you are using the correct SPI mode for your transfer (CPOL, CPHA)
4. During that time there is a reset. -> Can you please elaborate this condition. Does this mean the device (PSoC or Slave) is getting reset? Or is the CS line going high in between the transaction?
5. What is the data rate used? Does this issue happen when you reduce the data rate?
6. We checked the SPI communication and saw that there SPI transfers happening with a fixed timing behavior and some SPI transfers jitter with a slightly shift to these-> Please share screenshots of the scope
7. A possible impact could be that after some time, the SPI transfers overlapping, so that a next transfer or callback is called without clearing the buffer before. -> Please share the code.