1 Reply Latest reply on Nov 11, 2019 9:51 PM by BragadeeshV_41

    SPI communication issue in CYPRESS PSOC4.2

    hish_4569026

      Hello,

      I am facing a problem with spi communication between two microcontrollers. i.e TI microcontroller and Cypress, where cypress is master, TI is slave, I see a reset issue which does not occur always.

      SPI payload data is 13 bytes long.  When the data is sent from master to slave,data sent from master to slave is not as expected, and during that time there is a reset. I have checked that baud rate, it is same on both the sides.

      SPI is  4-wired. MISO, MOSI,CLK,. Chip Select (low active).

      Another observation:

      We checked the SPI communication and saw that there SPI transfers happening with a fixed timing behavior and some SPI transfers jittering with a slightly shift to these. A possible impact could be that after some time, the SPI transfers overlapping, so that a next transfer or callback is called without clearing the buffer before.

      Please provide solution to the above problem.

      Thanks in advance.

       

        • 1. Re: SPI communication issue in CYPRESS PSOC4.2
          BragadeeshV_41

          Hi hish_4569026,

           

          1. Please probe the bus and share the screenshots of the issue your are facing.

          2. Send us a project that focuses on the issue so that we can reproduce the issue from our end. This is important to understand your issue and provide a solution. To send the project, refer to Archiving a PSoC Creator Design.

          3. Check you are using the correct SPI mode for your transfer (CPOL, CPHA)

          4. During that time there is a reset. -> Can you please elaborate this condition. Does this mean the device (PSoC or Slave) is getting reset? Or is the CS line going high in between the transaction?

          5. What is the data rate used? Does this issue happen when you reduce the data rate?

          6. We checked the SPI communication and saw that there SPI transfers happening with a fixed timing behavior and some SPI transfers jitter with a slightly shift to these-> Please share screenshots of the scope

          7. A possible impact could be that after some time, the SPI transfers overlapping, so that a next transfer or callback is called without clearing the buffer before. -> Please share the code.

           

          Regards,

          Bragadeesh