Thank you for contacting Cypress Technical support.
Can you please attach a screenshot of the error window?
Can you please attach your project so that we reproduce the error at our side this will help us get better insight of the issue/
Are you using clock inside the module?
Or how about modifying the line
assign T = ((a & b) | (b & c) | (c & a)) ;
always @ (posedge clock) begin
T <= ((a & b) | (b & c) | (c & a)) ;
Thank you for the input moto.
Carlos can you implement the changes suggested by moto. The user clock drives the blocks in the UDB therefore you need to use clock for driving the logic in your project.
I have attached a project implementing the changes suggested by moto and the project is building fine.
Please have a look at it.
Thanks and Regards
test_project.cyprj.Archive01.zip 485.9 K