4 Replies Latest reply on Nov 10, 2019 10:46 PM by BragadeeshV_41

    Is there a proper way to determine if the Transmit of data is FULLY complete using the PDL UART component?


      I'm writing code for a PSoC6 and I'm using the PDL SCB_UART for debugging.  In the application, I go to DeepSleep as often as I can to save battery power.


      When I am dumping debug data to the SCB_UART many times the PSoC goes into DeepSleep mode before the Transmit Data is completely sent.  This causes partial data in the terminal as well as framing errors.


      I can perform a CyDelay() with some time to eliminate this, but I'd prefer to query if the Transmit is fully complete before going to DeepSleep.  The CyDelay is open loop and has to be calibrated to work across all data.  I'm looking for a closed loop method.


      I've tried

      while((UART_GetNumLeftToTransmit() > 0)){}    // Wait until ALL Tx byte sent.

      No luck.

      I've also tried

      while((UART_GetNumInTxFifo() > 0)){}    // Wait until ALL Tx byte sent.

      Still no luck.

      I've also tried

      while((UART_GetTransmitStatus() & CY_SCB_UART_TX_DONE) != true){}    // Wait until ALL Tx byte sent.

      This was worst than the first two.


      I think in the first 2 cases, it only reports 0 when there are no bytes in the FIFO but the last data is in the serial buffer.


      Any suggestions?