4 Replies Latest reply on Nov 20, 2019 10:11 PM by SudheeshK_26

    HyperRam communication problem in MCP

    omgu_4560031

      Hello,

       

      We have designed an FPGA board and now testing it. There are S71KS512SC0BHV00 MCP (HyperRam HyperFlash) and S70KS1281DPBHI02 HyperRam on it. We have successfully run S70KS1281DPBHI02 HyperRam at 150 Mhz but have some problems about S71KS512SC0BHV00 MCP. Now, we are trying to do memory test with HyperRam in MCP. We could do successfull transfers when clock is 50 Mhz and Burst size is 8. But when we increase the burst size (such as 16 or more) or clock rate ( such as 100 Mhz ), our test fails. The interesting thing is that the lower byte of 16 bit read data is always correct but higher byte is problamatic. Do you have any suggestions about this problem? I have two test boards and observe similar behaviour. By the way, we don't do any operation to HyperFlash in MCP. Drived CS#1 signal to logic '1'.

       

      Best regards, Omer

        • 1. Re: HyperRam communication problem in MCP
          SudheeshK_26

          Hi,

           

          We would like to know some more details about this issue. Could you please provide below details?

           

          1. Could you please provide the sequence of operations that you perform in your test?

          2. Which is the FPGA that you use in your application? Are you using HyperBus controller IP from Cypress?

          3. Can you capture and provide logic analyzer waveform for read and write operations to HyperRAM in the MCP device?

           

          Thanks and Regards,

          Sudheesh

          • 2. Re: HyperRam communication problem in MCP
            omgu_4560031

            Hello Sudheesh,

             

            I couldn't load this document to form. So, sent by email. You can find answers to your question in the form.

             

            Best regards,

            Omer Gunay

            • 3. Re: HyperRam communication problem in MCP
              omgu_4560031

              Hello Sudheesh,

              Thank you very much for your help.

               

              You can find answers to your questions in below,

               

              Answer Q1:

              Firstly, we start the test by writing below pattern in memory and then read and check this pattern.

              Addr  Data
              0x0  0x0000
              0x1  0x0001
              0x2  0x0002
              .  .
              .  .
              0xC800  0xC800

               

              After this pattern, we incerase all data content by 1 and check again. This test continues until the first data gets 0x3FFF. After 0x3FFF it becomes 0x0000 again and continue.

               

              Answer Q2:

              We are using Microsemi Polarfire FPGAs and using our own HyperBus controller. We tested this code with Altera Cyclone 10 LP development board and also as I said before, the HyperRam (S70KS1281DPBHI02 ) on the same board could be communicated with this code. Our codes are purely VHDL and does not include any vendor specific IP.

               

              Answer Q3:

              I have loaded a word document. It includes some FPGA hardware debug ( Microsemi Identify tool is used) pictures to help you.

               

              Best regards,

              Omer

              • 4. Re: HyperRam communication problem in MCP
                SudheeshK_26

                Hi Omer,

                 

                To debug this issue further, can you please perform below test and let us know the results?

                 

                1. Write in 8 burst at 50MHz and read in 16 burst at 100MHz

                2. Write in 16 burst at 100MHz and read in 8 burst at 50MHz

                 

                Thanks and Regards,

                Sudheesh