2 Replies Latest reply on Jul 14, 2015 12:32 AM by fishc_1849816

    Typo in "WICED Smart Hardware Interfaces" document

      MMP920732HW-AN101-R - page 8, paragraph 3:

      The maximum SCLK speed supported by SPIFFY1 is 12 MHz in all clock modes. This assumes that the IO

      supply rail can be guaranteed to be 2.4V. When the IO supply is 2.4V, then the SPIFFY1 SCLK is limited to

      6 MHz operation.


      I believe one of those should be ">"