9 Replies Latest reply on Oct 25, 2019 4:31 AM by AH_96

    Issue with the P3_0 and P3_1 pins on CY8CKIT-042

    sag_4314046

      Hi,

           I am using CY8CKIT-042 PSoC® 4 Pioneer Kit for connecting 10 Cap sense buttons and 2 Cap sense sliders (each consisting of 6 sensors). As i am lagging with GPIO pins on the PSoC kit i used P3_1 and P3_0 pins for taking input from two sensors of one slider.

       

      Actually these pins(P3_1 and P3_0) are used for the I2C communication of the Cap sense tuner. But for this project we need tuner also, so for now i am enabling tuner by connecting P3_1 and P3_0 pins to SDA and SCL pins respectively for noting down the signal values (when Cap sense module is being touched) and after that i am disconnecting P3_1 and P3_0 pins from tuner and assigning back to the Slider sensors.

       

      when i am following the above mentioned procedure i am unable to get the signal from the sensors connected to P3_1 and P3_0 pins(2 sensor pins of slider) and if i Reset the PSoC kit (with the help of the Reset button on PSoC board)then i am able to get the signal from both the pins (P3_1 and P3_0).

       

      My queries are:

      1. Can i know about the issue regarding above mentioned query?

      2. I have attached the pin assignment of my project. Kindly help me if i can use any other pins instead of P3_1 and P3_0 for the sensors of slider.

      3. I tried to use P12_6 and P12_7 pins on J8 header, but in the PSoC creator under Pin assignment in am not getting any option of P12_6 and P12_7 pins. Is that possible to use P12_6 and P12_7 pins. If yes, Kindly suggest me how to use it.

       

      Please let me know asap as it a serious and urgent issue.

       

      Thanks in advance.

        • 1. Re: Issue with the P3_0 and P3_1 pins on CY8CKIT-042
          MoTa_728816

          Hi,

           

          May be this is a last resort, but if you can give up debugging you can use P3[2] and P3[3].

           

          In the system, select GPIO for Debug Select

          000-System.JPG

          Then assign P3[2] and P3[3] for CapSense

          Note: I could assign, but I have not tested.

          001-P3_2_P3_3.JPG

           

          moto

          2 of 2 people found this helpful
          • 2. Re: Issue with the P3_0 and P3_1 pins on CY8CKIT-042
            sag_4314046

            Thanks moto for the reply.

             

            It's helpful. I will check it by using P3[2] and P3[3] pins.

             

            Can u also help me out regarding different behaviour of P3_1 and P3_0 pins about which i mentioned in the above query?

             

            Thank you.

            • 3. Re: Issue with the P3_0 and P3_1 pins on CY8CKIT-042
              MoTa_728816

              Hi,

               

              I looked at the schematic, P3_1 and P3_0 can be pulled-up from KitProg's PSoC 5LP.

              But I assume that this capability will be used only when I2C Bridge is used.

              So I wondered why this symptom appears.

               

              A couple of questions came up to my mind

              (1) Where and how do you pull-up those pins when you use them as I2C?

              (2) There may be some memory effect taking place in side the port.

               

              (1) How do you apply pull-up resistors when you use P3_1 and P3_0 for I2C?

               

              (2) Recently YuMa-san posted a method to reset I2C Slave from I2C Master,

              to do so, pin's mode was changed from OpenDrain to GPIO and used to drive the line.

              The topic's URL is

              Regarding PSoC4 I2C reset for I2C slave hang up(SDA is low)

               

              May be you can try changing the drive mode of P3_1 and P3_0 to GPIO

              before trying to use them for CapSense.

               

              Note: I imagine that the open-drain port must have been driven to high from external signal while they were I2C,

              so I would try to change the drive mode to strong drive then write value 0 to discharge any remaining current.

              Then use them as CapSense. (This is my idea and I have not tested it.)

               

              moto

              • 4. Re: Issue with the P3_0 and P3_1 pins on CY8CKIT-042
                TaH_4345166

                Hi MoTa_728816,

                Actually we are not externally applying pull-up resistor when we use P3_0 and P3_1.

                 

                We have to use the Tuner for tuning CapSense. for that purpose, we have add EZI2C component in our project to use Tuner.

                 

                So pin configuration requires for SCL and SCK when I use EZi2C and we have used P3_0 and P3_1 for the same.

                 

                But when we are done with Tuner, we need to use the same pins for CapSense.

                 

                So, can we get any settings or code to set these 2 pins(p3_0 & p3_1) as CSD pins instead of EZI2C pins by default. Any configuration register code is also fine.

                 

                By the way ,how any pin used in the project is configured as input/output or even I2C or CapSense pins? Do we have to externally write any code for selecting particular alternative function as described in data sheet.

                https://community.cypress.com/servlet/JiveServlet/showImage/2-212991-431095/pastedImage_0.png

                • 5. Re: Issue with the P3_0 and P3_1 pins on CY8CKIT-042
                  BoTa_264741

                  Moto,

                  where are the pins 3.2 and 3.3 on the CY8CKIT-042?

                  /odissey1

                  • 6. Re: Issue with the P3_0 and P3_1 pins on CY8CKIT-042
                    MoTa_728816

                    Dear /odissey1-san,

                     

                    > where are the pins 3.2 and 3.3 on the CY8CKIT-042?

                    Of course, they are .... OOPS!

                     

                    Well, if I may say...

                    P3[2] SWDIO is connected to J6-2

                    P3[3] SWDCLK is connected to J6_4

                    So it is not impossible to access them but may not be easy to access.

                     

                    Thank you for the point out!

                     

                    Best Regards,

                    25-Oct-2019

                    Motoo Tanaka

                    • 7. Re: Issue with the P3_0 and P3_1 pins on CY8CKIT-042
                      AH_96

                      Hi,

                       

                      The pull up resistors are present as a part of the kit and these are soldered on the board. Therefore, these pull up resistors are present and need not be connected externally.

                       

                      Regarding the process mentioned in the thread, let me know how you are changing the pin mode from EZI2C to CapSense. Are these two separate projects (one without the two slider segments and one with two slider segments and i2c)? Or are you changing the source dynamically at run-time?

                       

                      Also, from the picture shared, I can see that you are using P4[0] and P4[1] for I2C (not P3[0] and P3[1]) and the pin configurations are valid. you can use a USB to I2C bridge to observe the tuner values or you can assign P3[0] and P3[1] to I2C and P4[0] and P4[1] to CapSense. Please elaborate on the problem that you are facing.

                       

                      Thanks and regards

                      Hari

                      • 8. Re: Issue with the P3_0 and P3_1 pins on CY8CKIT-042
                        TaH_4345166

                        Hi Hari,

                        Thanks for the response.

                         

                        We are not using 2 separate projects. In a single project itself, we have both the components as in layout attached in first thread.

                         

                        Only thing is as I have 10 buttons and 12 slider sensors, initially I assign the P3_0 & P3_1 to EZI2C:scl & EZI2C:SDA respectively. Meantime I will not be connecting my capsense for RightSlider_Sns1 & RightSlider_Sns2 pins. Instead I will use auto assign of pins so that system assigns some left out pins automatically. Now I get the Signal values for all sensors except these sensors and I will tune.

                         

                        Once tuning is done and capsense sensitivity & response is good, I will assign pins P3_0 and P3_1 to RightSlider_Sns1 & RightSlider_Sns2 pins. And I will connect my hardware to those 2 pins.

                        So this is the process, I am following in the project.

                         

                        So after re-assigning the pins to slider pins & flashing the software. Pins P3_0 & P3_1 are not responding. SO I needed to reset the hardware couple of times to work. But in one more system these pins are not sensing at all.

                         

                        That's the abnormal behavior we are seeing using these 2 pins. That's why, we thought may be system is considering P3_0 and P3_1 as I2C pins and not sensing.

                         

                        So any process/code to set these 2 pins as CSD pins by default. So these 2 pins sense in-conditionally.

                        • 9. Re: Issue with the P3_0 and P3_1 pins on CY8CKIT-042
                          AH_96

                          Hi TaH_4345166

                           

                          Thank you for the explanation.

                           

                          As the kit schematic shows, there are pull up resistors present on the I2C lines. This will interfere with the CapSense operation. This is why you are not observing CapSense operation, and not due to I2C component interference.

                           

                          You can instead, use P4[0] and P4[1] as CapSense pins by removing R8 and R9 (pull up resistors used for I2C). Please note that a 560 ohm series resistor is recommended.

                           

                          Do let us know if this is viable in your design.

                           

                          Thanks and regards

                          Hari