Thanks moto for the reply.
It's helpful. I will check it by using P3 and P3 pins.
Can u also help me out regarding different behaviour of P3_1 and P3_0 pins about which i mentioned in the above query?
I looked at the schematic, P3_1 and P3_0 can be pulled-up from KitProg's PSoC 5LP.
But I assume that this capability will be used only when I2C Bridge is used.
So I wondered why this symptom appears.
A couple of questions came up to my mind
(1) Where and how do you pull-up those pins when you use them as I2C?
(2) There may be some memory effect taking place in side the port.
(1) How do you apply pull-up resistors when you use P3_1 and P3_0 for I2C?
(2) Recently YuMa-san posted a method to reset I2C Slave from I2C Master,
to do so, pin's mode was changed from OpenDrain to GPIO and used to drive the line.
The topic's URL is
May be you can try changing the drive mode of P3_1 and P3_0 to GPIO
before trying to use them for CapSense.
Note: I imagine that the open-drain port must have been driven to high from external signal while they were I2C,
so I would try to change the drive mode to strong drive then write value 0 to discharge any remaining current.
Then use them as CapSense. (This is my idea and I have not tested it.)
Actually we are not externally applying pull-up resistor when we use P3_0 and P3_1.
We have to use the Tuner for tuning CapSense. for that purpose, we have add EZI2C component in our project to use Tuner.
So pin configuration requires for SCL and SCK when I use EZi2C and we have used P3_0 and P3_1 for the same.
But when we are done with Tuner, we need to use the same pins for CapSense.
So, can we get any settings or code to set these 2 pins(p3_0 & p3_1) as CSD pins instead of EZI2C pins by default. Any configuration register code is also fine.
By the way ,how any pin used in the project is configured as input/output or even I2C or CapSense pins? Do we have to externally write any code for selecting particular alternative function as described in data sheet.
where are the pins 3.2 and 3.3 on the CY8CKIT-042?
> where are the pins 3.2 and 3.3 on the CY8CKIT-042?
Of course, they are .... OOPS!
Well, if I may say...
P3 SWDIO is connected to J6-2
P3 SWDCLK is connected to J6_4
So it is not impossible to access them but may not be easy to access.
Thank you for the point out!
The pull up resistors are present as a part of the kit and these are soldered on the board. Therefore, these pull up resistors are present and need not be connected externally.
Regarding the process mentioned in the thread, let me know how you are changing the pin mode from EZI2C to CapSense. Are these two separate projects (one without the two slider segments and one with two slider segments and i2c)? Or are you changing the source dynamically at run-time?
Also, from the picture shared, I can see that you are using P4 and P4 for I2C (not P3 and P3) and the pin configurations are valid. you can use a USB to I2C bridge to observe the tuner values or you can assign P3 and P3 to I2C and P4 and P4 to CapSense. Please elaborate on the problem that you are facing.
Thanks and regards
Thanks for the response.
We are not using 2 separate projects. In a single project itself, we have both the components as in layout attached in first thread.
Only thing is as I have 10 buttons and 12 slider sensors, initially I assign the P3_0 & P3_1 to EZI2C:scl & EZI2C:SDA respectively. Meantime I will not be connecting my capsense for RightSlider_Sns1 & RightSlider_Sns2 pins. Instead I will use auto assign of pins so that system assigns some left out pins automatically. Now I get the Signal values for all sensors except these sensors and I will tune.
Once tuning is done and capsense sensitivity & response is good, I will assign pins P3_0 and P3_1 to RightSlider_Sns1 & RightSlider_Sns2 pins. And I will connect my hardware to those 2 pins.
So this is the process, I am following in the project.
So after re-assigning the pins to slider pins & flashing the software. Pins P3_0 & P3_1 are not responding. SO I needed to reset the hardware couple of times to work. But in one more system these pins are not sensing at all.
That's the abnormal behavior we are seeing using these 2 pins. That's why, we thought may be system is considering P3_0 and P3_1 as I2C pins and not sensing.
So any process/code to set these 2 pins as CSD pins by default. So these 2 pins sense in-conditionally.
Thank you for the explanation.
As the kit schematic shows, there are pull up resistors present on the I2C lines. This will interfere with the CapSense operation. This is why you are not observing CapSense operation, and not due to I2C component interference.
You can instead, use P4 and P4 as CapSense pins by removing R8 and R9 (pull up resistors used for I2C). Please note that a 560 ohm series resistor is recommended.
Do let us know if this is viable in your design.
Thanks and regards