There is a current load from Sparkfun based on PSoC5LP, which does that
The project is open- source, you can download it from the GitHub. I tested the kit and It works up to 4A. There is not much there but a FET and load resistor, so you can save money and do it yourself.
I use the Constant Current Load (CCL) configuration ALL the time! You're configuration is fairly solid. I would consider two changes.
First: The DAC doesn't need to exit the PSoC. It can all be done with internal wiring using a VDAC. Less external wiring! Woo-Hoo!
Second: The CCL loading I tend to use is usually less than 100mA. Therefore a NPN transistor is more practical than a FET. In your case, you want to drive up to 4A. A FET provides a lower Rdson than the general NPN Vce_sat. However, even using analog FETs, the Vgate from cutoff to saturation is pretty narrow. Therefore the Opamp control range for the full spread of 0.1A to 4A is going to be challenging.
Driving a base of an NPN transistor might be a bit more accurate since the transistor gain is based on current which you can control with the base drive resistor. With an Hfe of 200, you can drive 20mA (Ibe) into the base to achieve 4A (Ice).
Whether you use a FET or NPN, thermal considerations will be a big challenge. For the FET, your worst-case Pd will be Ids^2*Rfet where Ids=4A => 4^2*Rfet = 16*Rfet watts.
The same issue for the NPN. The equivalent to Rfet is not usually listed in the datasheet. If Rfet = 1 ohm, then Pd = 16W.
\odissey1's link shows a PSoC controlling a FET with a big heatsink.
My general rules in design of power circuits:
- I prefer a transistor if trying to control the output in a linear mode across the range of control. Again, transistors have a wide range of control from Icutoff to Isaturation.
- I prefer a transistor if I use the output as a slow switch. You can find very low Vce_sat transistors (Onsemi has a number of them) to minimize the device PD when On.
- I prefer a transistor if low current loading (0 to 200mA) can be used as Fast PWM switch.
- I prefer a FET if high current loading (0 to 100A) can be used as Fast PWM switch. This is because you can get very low Rds_on FETs which significantly minimize the PD issues. I've driven up to 30A for 10 seconds with without the need of a heatsink.
I hope this helps.
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/odissey1's Gate_Drive_Tune circuits is creative but may be a bit difficult to tune at run-time when the ambient temperature changes or self-heat thermal effects of the FET occur.
Additionally, the control feedback loop on the Gain_Offset PGA requires constant SW intervention. Depending on your application for a constant current load, the additional latency may cause some control loop glitches.
Below is a CCL circuit I've used on the PSoC for projects to place a load for battery testing. It is tuned for 0mA to 100mA. It is very similar to your FET-based proposal. Since the feedback signal is connected to '-' input of the opamp, the control loop latency is dependant on the RC of the Rccl_fb_1 and the input capacitance of the PIN_ccl_fb_1 and the propagation delay of the OpAmp_ccl_1.
Carefully changing Rcs_1, Rccl_1 and Rccl_ctl_1 resistor values as well as a power transistor for Qccr_1 it should be possible to change the operational range from 0mA to 4A for your application.
Here's a current plot of the above circuit where I have commanded the CCL to 18mA for a duration of 1.04 secs.
Here's another perspective of the FET versus Transistor debate: In linear mode,
- Power dissipation is virtually identical for a FET or Transistor.
- Transistors have wider linear gain control between cutoff and saturation. That's why they are still used in Class A and Class AB amplifiers in audio.
- FET could have a slight edge over transistors with lower effective Rds @ saturation. This could mean lower Pd when driving the CCL at maximum load.
The schematic above is not mine, it is from Sparkfun's Variable Current Load original project. It somehow works, but I am not excited about the design and code.
My concern is that PSoC5 Opamps are not rail-to-rail, clipping ~100mV above GND. With sensing resistor 100mO, and current 0.5A, the Vminus of the Opamp_ccl_1 will be at 0.5A x 0.1Ohm = 50mV, which is below common range. Did you see any issues with that?
You are correct when the CCL setpoint is too low.
The goal of my design is that the value of Rccl_1 be high enough so that the lowest CCL set current be above the Opamp output offset you mention. However, not too high so that at maximum CCL set current, the voltage doesn't exceed Vdda of the PSoC.
A Rccl_1 should be chosen for the full range needed where the VDAC setpoint control can manage. The wider the full range of Voltage across Rccl_1, the more control resolution available. 7-, 8- or 12-bit (if using the dithered VDAC).
I've used a gain and offset calibration setting in EEPROM to allow for VDAC setpoint compensation to increase the load control accuracy.
In another application, I use the CCL to drive a 3V relay with the relay as the DUT in the configuration above. In my application, the VBAT power can be 3.5V to 30V and I set the CCL current at the spec current of the relay at 3V. Therefore even if VBAT goes to 30V, the relay only sees 3V because the relay coil is really a current driven device. The voltage spec is there because it is assumed the Power supply to the relay coil is constant. The CCL in the design prevents current overdrive and therefore prevents overvoltage.