11 Replies Latest reply on Oct 24, 2019 3:25 AM by MoPr_4537651

    PSoC 5LP DDS issue

    MoPr_4537651

      I am using the CY8CKIT-053 prototyping kit. I am using a very stable (1-2 ppm) 1 MHz external digital signal for clocking the PSoC. The clock is a 0-3.3V square wave. The PLL out frequency in my design is 80 MHz. I tried using the WaveDAC component configured as shown below to generate a 40 kHz sine wave. 1.PNG

      In the picture shown above the WaveDAC is actually configured for 45.249 kHz and the sample size is 136 and the sample rate is 6153.346 kSPS. Only in this configuration I am getting a sine wave of 39.95765 kHz.

       

      My question is

      Why is there such a big difference between what the PSoC creator shows and what actually comes out of the DAC. What should I do to rectify this issue?

        • 1. Re: PSoC 5LP DDS issue
          BoTa_264741

          mopr,

          You can use custom DDS component to obtain continuously tunable sine output. I recommend DDS32 and WaveDAC combination as shown in this thread

          DDS24: 24-bit DDS arbitrary frequency generator component

           

          /odissey1

          • 2. Re: PSoC 5LP DDS issue
            LePo_1062026

            mopr,

             

            I'll make an attempt to help here.  There is an advanced user extremely acquainted with DDS-related topics by the moniker of odissey1\.  Hopefully he'll spot this post.

             

            Your output is only as good as your input.  What is the ppm of your 1MHz crystal?   Have you measured the actual value of the crystal output?  (I recommend that you measure a buffered version of the signal and not the crystal input of output).   Can you share your project or at least your Clock DWR window?

             

            Additionally, the PLL has a jitter factor.  This is standard for a digital or analog PLL.  Jitter is due to a continuous tracking of the output to the input.  However, the nominal value should be a multiple of the input frequency.

             

            The PLL is a fractional-N type.  In this case, the denominator can be as high as 16 which gives a granularity of 1/16th.  Therefore a good fractional-N would be 40/1 with an input of 1MHz.

             

            Len

            • 3. Re: PSoC 5LP DDS issue
              BoTa_264741

              mopr,

              You can get a hint from this thread:

              Re: WaveDAC Half Frequency

               

              The issue is number of the bus clocks taken by DMA to transfer 1 byte. From my experiments it is 14 clocks. Therefore, maximum sample rate which WaveDAC8 can handle is 80MHz /14 = 5.7MHz. Your requested sample rate of 6.15MHz is beyond that DMA can handle, so it simply skips some cycles, making the output rate accidentally close to 40 kHz (while it should be ~45kHz).

              There are several solutions, the easy one is to reduce sample length (e.g. 128) and provide tunable clock by DDS32. Another solution is to use DDS24 with 8-bit bus and hardware sine table. Yet another solution is to use fixed clock (e.g. 1MHz) and make a software DDS). I recommend to start with DDS32 and WaveDAC8.

               

              For fast start you can use the signal generator from this project

              DelSig_ADC - Filter - VDAC streaming demo using DMA

              ADC-Filter-VDAC_01b_C.png

              It uses also a custom WaveGen8 component instead of WaveDAC8. It uses same principle of operation as WaveDAC8 but is slightly more stable at high frequency limit. The benefits of this approach is that CPU is not involved and reference signal is available. The drawback is that at high frequency it uses 100% of DMA resources.

               

               

              For more sophisticated example using DDS-like approach with double-buffering check this demo:

              Re: Audio signal generator: strange noise with headphones, no noise when connected to PC

              DDS_WaveGen_02a_B.png

              This is fixed-frequency DDS, which means that a single low-pass filter can be used to cover 0-100kHz output range. Also at 1 MHz clock, only about 10-20% of DMA resources are consumed. The drawback of this approach is that it loads CPU quite well and no reference signal is available.

              /odissey1

              1 of 1 people found this helpful
              • 4. Re: PSoC 5LP DDS issue
                LePo_1062026

                \odissey,

                 

                You rock!

                 

                Len

                • 5. Re: PSoC 5LP DDS issue
                  MoPr_4537651

                  Hey, this is awesome! I came across this when I was working with the PSoC 4200M a few months back. Since I couldn't use it back then, it had escaped my mind. Thanks a lot for bringing it to my attention again . Will definitely try this ASAP and let you know how it goes..

                  • 6. Re: PSoC 5LP DDS issue
                    MoPr_4537651

                    Hey, thanks for your inputs! Yes, I am aware of the jitters of the PLL. Right now, since I didn't have a TCXO I used a beaglebone black to generate a 1MHz signal. The ppm of the generated signal is between 1-2. It is a very stable signal. I will try out odisseys method and get back on this thread with more details

                    • 7. Re: PSoC 5LP DDS issue
                      MoPr_4537651

                      Oh yes, this makes sense. I was confused because I didn't really ask it to do 6.15 MHz. I asked it for 6 MHz and it set itself to 6.15 MHz. But you are right, I got your point. Thanks

                      • 8. Re: PSoC 5LP DDS issue
                        BoTa_264741

                        MoPr,

                        I added a link to the signal generator project in the above post.

                        /odissey1

                        • 9. Re: PSoC 5LP DDS issue
                          MoPr_4537651

                          BoTa,

                          I just finished using your DDS32 library. I took one of your example codes and modified it to only what was useful for me (Project is attached below). My aim was to generate a 40kHz sine wave. After I made a few changes to the frequencies I was able to get a frequency of 39.99965 kHz. I had to play around with the DDS_SetFrequency function to get that precision. I had to set it to 40067 Hz. This is very reasonable! I also noticed something very interesting. When I did a frequency spectrum analysis of the signal, I realized that the second harmonic is extremely suppressed (by about 100 times) as shown below. This is something which I didn't see in my previous attempt using the inbuilt components.

                          1.png

                          How did you manage to do this? I have never seen this kind of suppression without using some filters. I am very intrigued!

                          Thanks a lot for this awesome library

                          • 10. Re: PSoC 5LP DDS issue
                            BoTa_264741

                            MoPr,

                            In DDS32 basic dialog there is parameter "ClockFreq". For high precision it must be set to the actual (measured, not nominal) input clock value (for example 79.883E+6). Then DDS output will be exactly what is set in the output "Frequency" parameter (for example 40000). With XTAL-stabilized input 10-6 precision is achievable.

                             

                            I recommend to use DDS32 component, as it can run at 80MHz clock without warning. The DDS24 has more options, but is limited to about 56MHz BUS_CLK. I believe that to achieve 40kHz you want the highest bus frequency.

                             

                            The chart provided doesn't cover 80kHz range, not it has a logarithmic amplitude scale, I can't see harmonics either. Theoretically, for 8-bit sine wave maximum SFDR is approx -8(bit) x 6.02 - 3.92  = 52.08 dB (see attached paper). With 2-nd order multiple feedback LPF I see approx -50dB. What data acquisition hardware did you use to make the chart?

                             

                            /odissey1

                             

                            PS. Attached archive is damaged. Best way to share the project is to (1) Build->Clean; (2) File->Create Archive Bundle-> minimal; (3) open created archive and delete Generated_sourse folder. The resulting zip file should be ~10 times smaller.

                            • 11. Re: PSoC 5LP DDS issue
                              MoPr_4537651

                              BoTa,

                              Wow, this is very interesting. Thank you for all your help

                              Will certainly look into the DDS32 component.

                              PFA the project. I followed the steps you told.

                              Also, I should have mentioned. The y-axis scale is linear. The 40kHz wave was sampled at 100kHz, so the 80kHz component would get aliased and show up at 20 kHz. When I zoomed into the graph, the 20kHz component had an amplitude of around 6 whereas the 40kHz had an amplitude of about 1000.